Quasi-Monolithic Die Architecture for Dense 3D Interconnects
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Solution Overview
Problem
Current semiconductor manufacturing processes for monolithic ICs face challenges such as decreased performance due to circuit placement limitations on a planar surface, leading to longer delays and reduced manufacturing yield, as well as low vertical and lateral interconnect densities in existing interconnect technologies.
Innovation Solution
The implementation of quasi-monolithic die architecture, which involves coupling multiple IC dies with high-density interconnects, including die-to-die interconnects with a pitch of less than 10 microns, and using through-dielectric vias surrounded by dielectric material with angled interface seams, to enhance connectivity and optimize individual die design for specific functionalities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple IC dies are coupled with high-density interconnects to form quasi-monolithic architecture, then interconnect density and performance are improved, but manufacturing complexity and difficulty increase
Solution Approach 1:
The system divides the monolithic die into multiple separate IC dies (first die, second die, third die) that are coupled together through high-density interconnects. This segmentation allows each die to be manufactured independently with optimized functionalities while achieving high interconnect density through the coupling structure, resolving the contradiction between improved interconnect density and manufacturing complexity.
Solution Approach 2:
The patent implements a nested structure where multiple IC dies are hierarchically coupled - the first die couples to the second die, which in turn couples to the third die, forming a nested architecture. This nested doll approach enables systematic organization of complex multi-die systems, making the manufacturing process more manageable while achieving high interconnect density across all dies.
2Ease of manufacture
If circuits are placed on a planar surface in traditional monolithic ICs, then manufacturing is simplified, but performance decreases due to placement limitations and longer delays
Solution Approach 1:
The patent transitions from traditional planar (2D) circuit placement to a three-dimensional stacked architecture where multiple IC dies are vertically coupled. This dimensional change allows circuits to be arranged in multiple layers and levels, significantly reducing placement limitations and signal delays while maintaining manufacturing feasibility through standardized die coupling processes.
Solution Approach 2:
By segmenting the monolithic die into multiple separate IC dies with specialized functionalities (processing die, memory die, I/O die), the system enables optimized circuit placement on each individual die surface. This segmentation allows each die to be manufactured using simplified planar processes while achieving superior overall performance through the integrated multi-die architecture.
3Device complexity
If traditional interconnect technologies are used, then device complexity is reduced, but vertical and lateral interconnect densities remain low
Solution Approach 1:
The patent employs both vertical interconnects (through-silicon vias connecting stacked dies) and lateral interconnects (trace routes on die surfaces), creating a three-dimensional interconnect network. This multi-dimensional approach dramatically increases both vertical and lateral interconnect densities compared to traditional planar technologies, while maintaining manageable device complexity through standardized interconnect structures.
Data Source
AI summary
Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die and a through-dielectric via (TDV) surrounded by a dielectric material in a first layer, where the TDV has a greater width at a first surface and a smaller width at an opposing second surface of the first layer; a second die, surrounded by the dielectric material, in a second layer on the first layer, where the first die is coupled to the second die by interconnects having a pitch of less than 10 microns, and the dielectric material around the second die has an interface seam extending from a second surface of the second layer towards an opposing first surface of the second layer with an angle of less than 90 degrees relative to the second surface; and a substrate on and coupled to the second layer.