Quasi-Nonvolatile Memory Circuitry for Binarized Neural MACs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing von Neumann-based computing systems face bottlenecks due to the separation of processor and memory, leading to high energy consumption and latency, and current Logic In Memory (LIM) technologies using nonvolatile memory devices suffer from complex processes, low integration, and inability to perform all CMOS logic operations in a single cell.
Innovation Solution
A binarized neural network circuitry utilizing quasi-nonvolatile memory devices with a diode structure in the channel region, implementing memory and switching functions in a single device through a positive feedback loop, allowing simultaneous memory and logical operations with excellent uniformity and stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If von Neumann-based computing systems are used with separated processor and memory, then data processing can be performed, but energy consumption is high and latency is long due to physical separation
Solution Approach 1:
The patent merges memory and logic functions into a single device by integrating a diode structure within the memory device's channel region. This allows the same physical structure to perform both data storage and logical operations, eliminating the need for separate processor and memory components and reducing energy consumption associated with data transmission between them.
Solution Approach 2:
The memory device is designed to perform multiple functions: it can store data in its memory region and simultaneously perform logical operations (AND, OR, NOT, XOR, XNOR) through the diode structure in its channel region. This multi-functionality allows a single device to replace what would traditionally require separate memory and logic units.
2Adaptability or versatility
If Logic In Memory technology uses nonvolatile memory devices, then computational and memory functions are combined, but the process becomes complex due to non-silicon materials and device uniformity is low
Solution Approach 1:
The patent uses a silicon-based diode structure that is compatible with standard CMOS manufacturing processes. By employing materials and structures that are homogeneous with existing semiconductor fabrication techniques, the invention avoids the complexity associated with non-silicon materials while maintaining the ability to perform both memory and logic functions.
3Productivity
If LIM technology uses transistors for logic operations, then computational functions are performed, but bottlenecks and power consumption occur since logic and memory functions are not performed simultaneously
Solution Approach 1:
The patent combines memory storage and logic operations within the same device structure, allowing simultaneous execution of both functions. The diode structure in the channel region enables logical operations to be performed on data while it is stored in memory, eliminating the need to transfer data between separate memory and logic units and thereby reducing power consumption and bottlenecks.
4Adaptability or versatility
If individual circuits and wiring are required for each logic operation in LIM technology, then specific logic functions can be implemented, but integration is low
Solution Approach 1:
The diode structure within the memory device serves as a universal logic unit that can perform multiple logic operations (AND, OR, NOT, XOR, XNOR) depending on the applied voltages. This eliminates the need for separate dedicated circuits for each logic operation, thereby increasing integration density while maintaining versatility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The circuitry reduces standby power and increases computational efficiency with low power consumption, enabling next-generation artificial intelligence computing by performing memory and switching functions in a single device with excellent uniformity and stability.
Implementation Method 1
memory characteristics of remembering a memory state are implemented as holes or electrons in a potential well in the channel region due to the positive feedback loop are accumulated
Implementation Method 2
an operation state is determined by occurrence of a latch-up or latch-down phenomenon due to a positive feedback loop in the channel region based on different voltages applied to the drain terminal and the gate terminal
Data Source
AI summary
Disclosed is a binarized neural network circuitry using a quasi-nonvolatile memory device. More particularly, the binarized neural network circuitry according to an embodiment of the present disclosure is characterized in that a diode structure is positioned in a channel region between a drain terminal and a source terminal, a gate terminal is positioned on the diode structure, an operation state is determined by occurrence of a latch-up or latch-down phenomenon due to a positive feedback loop in the channel region based on different voltages applied to the drain terminal and the gate terminal, respectively, and a plurality of quasi-nonvolatile memory devices that implement memory characteristics of remembering a memory state are included as holes or electrons in a potential well in the channel region due to the positive feedback loop are accumulated, and the plural quasi-nonvolatile memory devices are a pair of two quasi-nonvolatile memory devices that operate as a single synaptic cell and are connected in parallel to form an array circuit, memory states of the two quasi-nonvolatile memory devices are determined and stored based on an input line applied from an input line processor connected to the array circuit and a weight update signal applied from a synaptic line processor connected to the array circuit, and a MAC (multiply-accumulate) operation result is output using a combination of the memory states.