Quasi-Nonvolatile Memory Synapses for Binarized Neural XNOR Computing
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Solution Overview
Problem
Existing von Neumann-based computer systems face bottlenecks due to the separation of processor and memory, leading to inefficiencies in data processing speed, power consumption, and integration, particularly in data-intensive applications like AI and IoT, and current Logic In Memory (LIM) technologies using nonvolatile memory devices suffer from complex processes, low integration, and inability to perform CMOS logic operations in a single cell.
Innovation Solution
A binarized neural network circuitry utilizing quasi-nonvolatile memory devices that perform both memory and switching functions in a single device through a positive feedback loop, enabling self-activation and stable operation, with synaptic cells composed of pairs of quasi-nonvolatile memory devices connected in parallel to perform XNOR logic operations and MAC operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If von Neumann-based computer systems are used with separated processor and memory, then data processing speed and integration are improved, but power consumption increases and data transmission latency occurs
Solution Approach 1:
The patent merges memory and logic functions into a single integrated circuit device, eliminating the physical separation between processor and memory. This integration allows data to be processed directly at the memory location without transmission through bus lines, thereby reducing power consumption while maintaining high data processing speed.
2Adaptability or versatility
If Logic In Memory technology is implemented using nonvolatile memory devices, then computational and memory functions are combined in the same space, but device uniformity and stability decrease
Solution Approach 1:
The patent employs a standardized circuit configuration where each memory cell consists of a uniform structure with a bit line, word line, and select transistor. This homogeneous design across all memory cells ensures consistent electrical characteristics and reliable operation, while still enabling both storage and logic functions through the same device structure.
3Adaptability or versatility
If non-silicon materials are used in Logic In Memory technology, then memory and switching functions can be combined, but manufacturing complexity increases
Solution Approach 1:
The patent utilizes standard silicon-based CMOS technology and modifies the operational parameters rather than changing the fundamental material composition. By adjusting voltage levels and timing parameters in the existing silicon process, the invention achieves both memory and switching functions without introducing manufacturing complexity associated with non-silicon materials.
4Ease of operation
If individual circuits and wiring are required for each logic operation, then logic operations can be performed, but integration density decreases
Solution Approach 1:
The patent designs a universal memory cell structure that can perform multiple logic operations (AND, OR, NOT, XOR) by varying the input signals and control line configurations. This multi-functional approach eliminates the need for separate dedicated circuits for each logic operation, thereby significantly increasing integration density while maintaining full logic operation capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces power consumption and computation time by integrating memory and logic functions, enhancing computational efficiency and stability, suitable for next-generation AI computing with low power consumption and high uniformity.
Implementation Method 1
an operation state is determined by occurrence of a latch-up or latch-down phenomenon due to a positive feedback loop in the channel region
Implementation Method 2
a plurality of quasi-nonvolatile memory devices that implement memory characteristics of remembering a memory state are included as holes or electrons in a potential well in the channel region due to the positive feedback loop are accumulated
Data Source
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AI summary
Disclosed is a binarized neural network circuitry using a quasi-nonvolatile memory device. More particularly, the binarized neural network circuitry according to an embodiment of the present disclosure is characterized in that a diode structure is positioned in a channel region between a drain terminal and a source terminal, a gate terminal is positioned on the diode structure, an operation state is determined by occurrence of a latch-up or latch-down phenomenon due to a positive feedback loop in the channel region based on different voltages applied to the drain terminal and the gate terminal, respectively, and a plurality of quasi-nonvolatile memory devices that implement memory characteristics of remembering a memory state are included as holes or electrons in a potential well in the channel region due to the positive feedback loop are accumulated, and the plural quasi-nonvolatile memory devices are a pair of two quasi-nonvolatile memory devices that operate as a single synaptic cell and are connected in parallel to form an array circuit, memory states of the two quasi-nonvolatile memory devices are determined and stored based on an input line applied from an input line processor connected to the array circuit and a weight update signal applied from a synaptic line processor connected to the array circuit, and a MAC (multiply-accumulate) operation result is output using a combination of the memory states.