Quasi-Vertical LDMOS Closed Cell Layout for Low On-Resistance
Solution Overview
Problem
Existing semiconductor technologies, such as LDMOS devices, face challenges in achieving low specific on-resistance (Rds,on) and efficient current handling for low voltage power applications, particularly in consumer portable electronic devices, due to high on-resistance and parasitic component values, which limit their performance and reliability.
Innovation Solution
A quasi-vertical MOS device with a closed cell configuration, such as a checkerboard or hexagonal arrangement, is implemented, featuring a doped substrate, thin epitaxial layer, conductive gate, and trench sinker for vertical current flow, which reduces on-resistance and avoids parasitic bipolar transistor activation by minimizing voltage drops and using a common doping type for body and substrate regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If LDMOS devices use thick epitaxial layers to achieve breakdown voltages >60V for RF applications, then breakdown voltage is improved, but on-resistance increases significantly
Solution Approach 1:
The patent changes the fundamental parameter of current flow direction from lateral to vertical, and reduces epitaxial layer thickness from thick to thin. This parameter transformation allows achieving low on-resistance with thin epitaxial layers while maintaining adequate breakdown voltage through the vertical junction structure, resolving the contradiction between breakdown voltage and on-resistance
Solution Approach 2:
The patent transitions from lateral current flow (2D plane) to vertical current flow (3D depth direction). This dimensional change enables the device to achieve breakdown voltage through vertical junction depth rather than through thick epitaxial layers, thereby reducing on-resistance while maintaining voltage handling capability
2Object-generated harmful factors
If LDMOS devices are arranged in stripe layout to minimize parasitic source inductance, then parasitic inductance is reduced, but de-biasing effect increases and current handling capability is limited
Solution Approach 1:
The patent changes the layout from lateral stripe arrangement to vertical closed-cell configuration. This dimensional reorganization allows current to flow vertically through the device structure, eliminating the de-biasing effect that occurs in lateral stripe layouts while maintaining low parasitic inductance through compact cell design
Solution Approach 2:
The patent segments the device into multiple vertical cells arranged in a closed-cell pattern, where each cell operates independently with vertical current flow. This segmentation eliminates the de-biasing effect between adjacent cells that plagues stripe layouts, allowing each cell to handle current without voltage drop to neighboring cells, thereby increasing overall current handling capability
Data Source
AI summary
A low voltage power device includes a plurality of quasi-vertical LDMOS device cells. A conductive trench sinker is formed through the epitaxial layer and adjacent a selected one of the source and drain regions in each cell. The trench sinker electrically couples the selected one of the source and drain regions to the substrate for coupling current from the channel to the substrate. The resulting device exhibits a vertical current flow between the metal electrode covering the front surface and the second electrode formed at the back side of the wafer. The device cells are arranged in a closed cell configuration.