Quasi-Volatile Memory Architecture for High-Density Low-Power Access
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Solution Overview
Problem
Conventional DRAM technology faces limitations in density improvement due to increased power consumption and heat dissipation as refresh rates increase, necessitating a new type of memory with higher density and lower power requirements.
Innovation Solution
The development of quasi-volatile memory (QV memory) systems, which utilize through-silicon vias and hybrid bonds to interconnect modular memory circuits on separate semiconductor substrates, allowing for lower refresh rates, reduced power consumption, and enhanced memory availability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If DRAM refresh rate is increased to maintain data, then data retention is improved, but power consumption increases
Solution Approach 1:
The patent changes the fundamental parameter of data retention mechanism from periodic refresh (DRAM) to charge trapping (QV memory). QV memory cells use a charge trapping layer that stores data charge for extended periods without refresh, fundamentally altering how data retention is achieved and eliminating the power consumption associated with periodic refresh operations.
Solution Approach 2:
The patent extracts the refresh function entirely from the memory system. By using charge trapping mechanisms, the memory cells can retain data without requiring periodic refresh cycles, removing the source of power consumption associated with maintaining data integrity in conventional DRAM.
2Quantity of substance
If DRAM capacitor size is reduced to increase density, then memory density is improved, but refresh rate must increase causing more power consumption
Solution Approach 1:
The patent changes the storage mechanism from capacitor-based charge storage to trap-based charge storage. The charge trapping layer allows for larger effective storage capacity without reducing cell size, as each cell can retain charge more effectively and for longer periods, enabling higher density without the compensating increase in refresh rate.
Solution Approach 2:
The patent introduces a vertical dimension to charge storage by implementing charge trapping layers stacked between word lines. This multi-layer charge trapping structure increases storage capacity in the vertical dimension without reducing the horizontal cell footprint, achieving higher density without increasing refresh requirements.
3Reliability
If DRAM refresh rate is increased to maintain data, then data retention is improved, but memory availability decreases
Solution Approach 1:
The patent removes the refresh operation from the memory system entirely. By using charge trapping mechanisms, data is retained passively without requiring periodic refresh cycles, eliminating the time during which memory is unavailable for host access and maximizing memory availability.
Solution Approach 2:
The QV memory cells serve themselves by automatically retaining data through charge trapping without external intervention. The trapped charge naturally maintains data integrity over extended periods without requiring refresh operations, making the memory self-sufficient and continuously available for host access.
4Reliability
If more memory units are refreshed in each cycle to maintain refresh rate, then data retention is maintained, but power consumption and heat dissipation increase
Solution Approach 1:
The patent fundamentally changes the data retention mechanism from active refresh to passive charge trapping. Instead of periodically restoring charge in capacitors, QV memory cells trap charge in a dedicated layer, eliminating the need for refresh operations entirely and the associated power consumption and heat dissipation.
Solution Approach 2:
The patent converts the natural charge leakage phenomenon, which is harmful in DRAM and requires refresh to correct, into a beneficial charge trapping mechanism. The charge trapping layer exploits the charge storage capability to maintain data indefinitely without refresh, turning what was a problem into the foundation of the solution.
Data Source
AI summary
A high-capacity system memory may be built from both quasi-volatile (QV) memory circuits, logic circuits, and static random-access memory (SRAM) circuits. Using the SRAM circuits as buffers or cache for the QV memory circuits, the system memory may achieve access latency performance of the SRAM circuits and may be used as code memory. The system memory is also capable of direct memory access (DMA) operations and includes an arithmetic logic unit for performing computational memory tasks. The system memory may include one or more embedded processors. In addition, the system memory may be configured for multi-channel memory accesses by multiple host processors over multiple host ports. The system memory may be provided in the dual-in-line memory module (DIMM) format.