Quasi-Volatile Memory Architecture With SRAM Buffering for Low-Power Density
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Solution Overview
Problem
Conventional DRAM technology faces limitations in density improvement due to increased power consumption and heat dissipation as refresh rates increase, necessitating a new type of memory with higher density and lower power requirements.
Innovation Solution
The development of quasi-volatile memory (QV memory) systems, which utilize through-silicon vias and hybrid bonds to interconnect memory circuits, allowing for modular organization and reduced refresh rates, enabling higher density and lower power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If DRAM refresh rate is increased to maintain data, then data retention is improved, but power consumption increases
Solution Approach 1:
The patent implements a reduced refresh rate mechanism where QV memory is refreshed less frequently than conventional DRAM (e.g., every 64ms or longer versus every few milliseconds). This periodic action with extended intervals leverages the inherent data retention capability of QV memory cells, significantly reducing the power consumption associated with refresh operations while maintaining data integrity.
Solution Approach 2:
The patent changes the fundamental parameter of data retention time by using QV memory technology with retention times exceeding 64 milliseconds, compared to conventional DRAM's shorter retention. This parameter change enables the system to operate with lower refresh rates, directly addressing the contradiction between data retention and power consumption.
2Quantity of substance
If DRAM capacitor size is reduced to increase density, then data density is improved, but refresh rate must increase causing more power consumption
Solution Approach 1:
The patent changes the retention time parameter of the memory medium itself by adopting QV memory technology. This fundamental parameter change allows achieving high data density without the need for frequent refreshes, thereby avoiding the power consumption penalty that would otherwise result from increased refresh rates.
3Reliability
If more memory units are refreshed in each cycle to maintain refresh rate, then data retention is improved, but heat dissipation increases
Solution Approach 1:
The patent implements extended refresh intervals for QV memory, performing refresh operations less frequently than conventional DRAM. This periodic action with longer cycles reduces the total number of refresh operations required across all memory units, thereby reducing cumulative heat generation while maintaining data retention through the inherent stability of QV memory cells.
Data Source
AI summary
A high-capacity system memory may be built from both quasi-volatile (QV) memory circuits, logic circuits, and static random-access memory (SRAM) circuits. Using the SRAM circuits as buffers or cache for the QV memory circuits, the system memory may achieve access latency performance of the SRAM circuits and may be used as code memory. The system memory is also capable of direct memory access (DMA) operations and includes an arithmetic logic unit for performing computational memory tasks. The system memory may include one or more embedded processor. In addition, the system memory may be configured for multi-channel memory accesses by multiple host processors over multiple host ports. The system memory may be provided in the dual-in-line memory module (DIMM) format.