Quaternized Dipyridyl Levelers for Void-Free Copper Via Filling
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Solution Overview
Problem
In semiconductor manufacturing, the challenge lies in achieving uniform copper deposition with minimal voiding and impurities in interconnect features, particularly as device sizes shrink, where conventional methods struggle with overplating, underplating, and microvoid formation due to the need for faster bottom-up growth rates and high purity copper deposits.
Innovation Solution
The introduction of quaternized dipyridyls as leveler additives in the electrolytic copper deposition chemistry enhances the deposition of high purity copper layers, inhibiting void formation and improving the aspect ratio filling capabilities, thereby reducing overplating and underplating issues while maintaining low impurity levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional electrolytic copper deposition is used to fill interconnect features, then copper can be deposited into the features, but overplating and underplating occur leading to non-uniform deposition
Solution Approach 1:
The patent introduces organic leveling agents as intermediary substances that mediate between the copper ions and the substrate surface. These agents adsorb preferentially on certain areas (field regions) to suppress deposition, while allowing enhanced deposition in interconnect features, thereby achieving uniform filling without overplating or underplating
Solution Approach 2:
The patent applies different deposition rates to different locations: suppressed deposition on field regions and enhanced deposition in interconnect features. This spatially varying deposition quality is achieved through the selective adsorption of leveling agents, creating locally optimized deposition characteristics for each region type
2Productivity
If faster bottom-up growth rates are used to fill interconnect features, then filling speed improves, but microvoid formation increases
Solution Approach 1:
The patent employs pulsed or periodic deposition cycles alternating between high-current-density phases (for rapid bottom-up filling) and low-current-density phases (for defect-free conformal deposition). This periodic modulation allows fast filling while preventing microvoid formation by periodically reducing stress and allowing uniform material distribution
Solution Approach 2:
The patent dynamically adjusts deposition parameters during the process, transitioning between different deposition modes (suppressed, enhanced, and conformal) based on real-time conditions. This dynamic control enables the system to achieve fast filling speeds while maintaining reliability by adapting to prevent void formation
3Quantity of substance
If electrolytic copper deposition is used to achieve high circuit density, then interconnect feature dimensions can be reduced, but impurity levels increase
Solution Approach 1:
The patent modifies deposition parameters including current density, temperature, pH, and additive concentrations to optimize the deposition process. These parameter changes enable high circuit density achievement while maintaining low impurity levels by controlling nucleation and growth conditions to favor pure copper deposition
Solution Approach 2:
The patent replaces conventional mechanical or chemical polishing methods with an electrochemical approach using leveling agents and pulsed deposition. This substitution achieves both high density and high purity by using electrochemical fields to selectively remove impurities and refine the copper deposit in-situ during deposition
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The use of quaternized dipyridyls in the electrolytic copper deposition chemistry results in copper layers with significantly reduced impurities and improved filling characteristics, leading to enhanced electromigration resistance, rapid room temperature crystallization, and lower microvoid formation, which addresses the challenges of voiding and impurity-related defects in semiconductor interconnect features.
Implementation Method 1
electrolytic copper deposition
Implementation Method 2
rapid room temperature crystallization
Implementation Method 3
rapid room temperature crystallization
Data Source
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AI summary
A method for metallizing a via feature in a semiconductor integrated circuit device substrate, wherein the semiconductor integrated circuit device substrate comprises a front surface, a back surface, and the via feature and wherein the via feature comprises an opening in the front surface of the substrate, a sidewall extending from the front surface of the substrate inward, and a bottom. The method comprises contacting the semiconductor integrated circuit device substrate with an electrolytic copper deposition chemistry comprising (a) a source of copper ions and (b) a leveler compound, wherein the leveler compound is a reaction product of a dipyridyl compound and an alkylating agent; and supplying electrical current to the electrolytic deposition chemistry to deposit copper metal onto the bottom and sidewall of the via feature, thereby yielding a copper filled via feature.