Qubit Coupling Structure With Trenches for Lower Parasitic Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Quantum computing devices face issues with parasitic capacitance and coupling to undesired modes, leading to decoherence and reduced coherence times due to the proximity of qubits to parasitic modes operating near their transition frequencies.
Innovation Solution
The introduction of trenches in the dielectric substrate with a lower electric permittivity than the substrate, adjacent to and/or underneath the superconductor layers, reduces parasitic capacitance and shifts the frequency of parasitic modes away from the qubit's resonant frequency, thereby minimizing unwanted coupling and decoherence.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If qubits are placed in close proximity to increase qubit density, then device integration is improved, but parasitic capacitance increases causing decoherence
Solution Approach 1:
A trench structure filled with air or vacuum (intermediary material) is introduced between the superconductor layer and the dielectric substrate. This intermediary reduces the parasitic capacitance between adjacent qubits while maintaining their close proximity for high density, thereby preserving coherence time.
Solution Approach 2:
The dielectric structure is modified locally by introducing trenches only in specific regions where parasitic capacitance is problematic. The trench depth and positioning are optimized to reduce capacitance locally without affecting the overall qubit coupling and density.
2Power
If qubits are placed near parasitic modes to achieve desired coupling, then coupling strength is improved, but unwanted coupling to parasitic modes increases causing decoherence
Solution Approach 1:
The trench structure modifies the local electromagnetic field distribution and shifts the resonant frequency of parasitic modes. By adjusting the trench depth, width, and positioning, the parasitic mode frequencies are shifted away from the qubit transition frequency, eliminating unwanted coupling while preserving desired qubit-qubit coupling.
3Ease of manufacture
If standard dielectric substrate is used for simplicity, then manufacturing is easier, but parasitic capacitance is high causing decoherence
Solution Approach 1:
The dielectric substrate is segmented by introducing trenches that divide the continuous dielectric into separated regions. This segmentation reduces the parasitic capacitance pathways while maintaining compatibility with standard fabrication processes, as the trenches can be formed using conventional lithography and etching techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces parasitic capacitance by up to 6.2 times, allowing for increased qubit density, reduced sensitivity to flux noise, and lower background dissipation levels, while maintaining inductance per unit length, thus enhancing the coherence times and operational flexibility of quantum computing devices.
Implementation Method 1
reduces parasitic capacitance by up to 6.2 times
Implementation Method 2
The trench has an electric permittivity that is less than an electric permittivity of the dielectric substrate
Implementation Method 3
The superconductor layer is formed from a superconductor material which exhibits superconducting properties at or below a corresponding critical temperature
Data Source
AI summary
A qubit coupling device includes: a dielectric substrate including a trench; a first superconductor layer on a surface of the dielectric substrate where an edge of the first superconductor layer extends along a first direction and at least a portion of the superconductor layer is in contact with the surface of the dielectric substrate, and where the superconductor layer is formed from a superconductor material exhibiting superconductor properties at or below a corresponding critical temperature; a length of the trench within the dielectric substrate is adjacent to and extends along an edge of the first superconductor layer in the first direction, and where the electric permittivity of the trench is less than the electric permittivity of the dielectric substrate.


