Superconducting Qubit Loop Crossing for Stronger Inductive Coupling
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Solution Overview
Problem
Existing quantum processors face limitations in performance due to constraints on the number of qubits and connectivity between them, which restrict the size and complexity of problems that can be solved, necessitating intermediate formulations to accommodate qubit architectures.
Innovation Solution
Implementing direct qubit-to-qubit coupling, combined with mediated coupling via a coupling device, to enhance the energy scale of the quantum processor, allowing for continuously variable tuning without increasing space requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If direct qubit-to-qubit coupling is implemented, then the energy scale and interaction strength are enhanced, but the device complexity and fabrication difficulty increase
Solution Approach 1:
The patent introduces a second vertical layer for qubit placement, enabling direct coupling between qubits in different layers through vertical proximity. This dimensional transition from planar to three-dimensional architecture allows strong interactions without increasing in-plane device complexity, as the coupling is achieved through vertical stacking rather than lateral expansion.
Solution Approach 2:
The patent employs coupling devices as intermediary elements that mediate interactions between qubits. These coupling devices can be positioned in the same layer or in intermediate layers, providing controlled coupling pathways that enhance interaction strength while maintaining manageable device complexity through modular coupling mechanisms.
2Quantity of substance
If the number of qubits is increased, then the problem size and complexity that can be solved increase, but the space requirements and device area expand
Solution Approach 1:
By transitioning to a multi-layer vertical architecture, the patent packs more qubits into a compact footprint. Qubits are arranged in multiple vertical layers, allowing the system to scale the number of qubits without proportionally increasing the device area, as the expansion occurs primarily in the vertical dimension rather than lateral spread.
Solution Approach 2:
The patent implements a nested arrangement where qubits in different layers are positioned to overlap or interdigitate in the planar projection. This nesting allows multiple qubits to occupy overlapping horizontal spaces at different vertical levels, effectively increasing qubit density without expanding the overall device footprint.
3Adaptability or versatility
If connectivity between qubits is enhanced, then the performance and problem-solving capability improve, but the space requirements and device complexity increase
Solution Approach 1:
The patent achieves enhanced connectivity by utilizing vertical coupling pathways between layers. Qubits in adjacent layers can be positioned in vertical alignment or close proximity, enabling direct coupling without requiring lateral coupling structures. This vertical connectivity approach increases the number of accessible neighbors for each qubit while maintaining compact in-plane dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances the energy scale and performance of quantum processors by enabling stronger ferromagnetic and antiferromagnetic interactions, overcoming limitations on problem size and complexity without space penalties.
Implementation Method 1
the first circuitous path and the second circuitous path are inductively proximate to each other for at least a portion of a length of the first circuitous path
Implementation Method 2
a first superconducting device comprising a first superconducting loop, the first superconducting loop comprising a first superconducting trace
Data Source
AI summary
A superconducting integrated circuit has a first superconducting device with a first superconducting loop, where the first superconducting loop has a first superconducting trace in a first layer of the superconducting integrated circuit, and a second superconducting device with a second superconducting loop, where the second superconducting loop has a second superconducting trace in a second layer. The first superconducting loop crosses the second superconducting loop in a crossing region. At least a portion of each of the first and the second superconducting trace inside the crossing region is narrower than at least a portion of each of the traces outside the crossing region, and follows a respective circuitous path which is inductively proximate to at least a portion of the other path.