Qubit Mapping via Weighted Graph QAP

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Solution Overview

Problem

Existing noisy intermediate-scale quantum (NISQ) devices face challenges in efficiently performing computationally demanding tasks due to limited qubit connectivity and increased noise from swap gate operations.

Innovation Solution

A method involving the creation of a weighted graph representing a quantum circuit, where qubits are nodes and connections are edges weighted by gate depth, is modeled as a Quadratic Assignment Problem (QAP) to determine an initial qubit mapping that minimizes noise and increases direct connections between qubits.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If qubits are sparsely connected in existing NISQ devices, then device complexity is reduced, but connectivity between qubits deteriorates requiring more swap gates

Engineering Contradiction:
Improvequbit connectivity structureVSAvoidqubit connectivity
Core Design Contradiction:
Device complexityVSEase of operation

Solution Approach 1:

The patent applies preliminary action by determining an initial qubit mapping before executing the quantum circuit. The system analyzes the quantum circuit description to identify qubit interactions and pre-assigns logical qubits to physical qubit locations, optimizing connectivity before the circuit runs. This preliminary mapping reduces the need for swap gates during execution.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces a mapping dimension that connects logical qubit space to physical qubit space. By creating this additional layer of abstraction, the system can optimize connectivity patterns without changing the physical hardware architecture. The mapping allows logical qubits to be assigned to physical qubits that minimize swap operations.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Ease of operation

If more swap gate operations are used to improve qubit connectivity, then ease of operation improves, but noise increases

Engineering Contradiction:
Improvequbit connectivityVSAvoidnoise
Core Design Contradiction:
Ease of operationVSObject-affected harmful factors

Solution Approach 1:

The system performs preliminary analysis of the quantum circuit to determine an optimal initial qubit mapping that minimizes swap gate requirements. By pre-planning qubit assignments based on expected interactions, the system reduces the total number of swap gates needed during circuit execution, thereby reducing noise.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system uses feedback from the quantum circuit description to optimize qubit mapping. By analyzing the circuit structure and qubit interaction patterns, the system adjusts the initial mapping to minimize swap operations. This feedback-driven approach ensures that qubits are positioned to reduce noise-generating swap gates.

Inventive Principle:
Principle #23Feedback

3Productivity

If computational tasks are performed on NISQ devices, then productivity is achieved, but reliability deteriorates due to limited qubit numbers and noise

Engineering Contradiction:
Improvecomputational capabilityVSAvoidcomputation accuracy
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The system determines an initial qubit mapping before circuit execution to optimize performance and minimize errors. By pre-optimizing qubit assignments based on circuit requirements, the system improves computational efficiency and reduces noise exposure, thereby enhancing both productivity and reliability.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system changes the mapping parameters that associate logical qubits with physical qubits. By optimizing these mapping parameters based on circuit characteristics, the system improves computation reliability without requiring additional qubits or hardware changes.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20250036994A1Quantum bit mapping
Publication Date: 2025.01.30 FUJITSU LTD
  • US20250036994A1 patent drawing
  • US20250036994A1 patent drawing
  • US20250036994A1 patent drawing

AI summary

A method may include obtaining a quantum circuit that includes quantum bits (qubits) that are sparsely connected such that a particular qubit may not include a physical connection to other qubits. The method may include generating a graph representing the quantum circuit in which a qubit is represented as a node and a physical connection between two qubits is represented as an edge. The method may include assigning weight values to the edges based on a respective gate depth to generate a weighted graph. An individual gate depth may indicate how early a particular operation of the quantum circuit associated with a respective edge is scheduled to be performed by the quantum circuit. The method may include modeling the weighted graph as a Quadratic Assignment Problem (QAP) and determining an initial mapping of the qubits based on a solution to the QAP.