3D Qubit Integration via Wafer Bonding and TSVs
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Solution Overview
Problem
Existing superconducting device technologies face challenges in achieving efficient three-dimensional integration of qubits with both vertical and planar Josephson junctions, and in maintaining the properties of crystalline silicon substrates during the manufacturing process, particularly when using Silicon-on-Metal (SOM) wafers, where the removal of bottom superconductor layers increases loss tangent, affecting quantum computing applications.
Innovation Solution
A superconducting structure is created by bonding patterned superconducting layers from multiple wafers, with through-silicon vias filled with superconducting metal, allowing for the integration of qubits with both vertical and planar Josephson junctions, and preserving the crystalline silicon substrate properties by pre-patterning the wafers to avoid etching through the entire structure, thus maintaining low loss tangent and coherence times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the bottom superconductor layer is removed using standard etch process, then the top superconductor layer can be kept for circuitry, but the loss tangent increases which is not preferred in quantum computing applications
Solution Approach 1:
The patent divides the superconductor structure into multiple discrete layers (first buried layer, second buried layer, and top superconductor layer) that can be independently patterned and bonded. This segmentation allows selective removal and replacement of specific layers without affecting others, enabling access to the bottom layer while preserving low-loss regions.
Solution Approach 2:
The patent changes the structural parameters by bonding wafers with different superconductor layer configurations. By varying the presence or absence of superconductor layers in different regions through the bonding process, the device achieves both access to bottom layer circuitry and maintenance of low loss tangent in quantum computing regions.
2Adaptability or versatility
If both thin and thick silicon layers are used, then vertical Josephson junctions and free configuration of interconnections can be achieved, but coupling across circuit layers on opposite sides of thin silicon surfaces increases
Solution Approach 1:
The patent applies different silicon layer thicknesses in different regions of the device. Thin silicon regions are used where vertical Josephson junctions are needed, while thick silicon regions are used where isolation between circuit layers is required. This local variation in thickness allows both vertical junction functionality and interconnection freedom while controlling unwanted coupling.
3Adaptability or versatility
If through-silicon vias are filled with superconducting metal, then vertical Josephson junctions can be formed, but the complexity of the manufacturing process increases
Solution Approach 1:
The patent performs pre-patterning of superconductor layers on wafers before bonding. Through-silicon via holes are created and partially filled with superconducting metal in advance, on separate wafers, before the bonding step. This preliminary preparation simplifies the overall manufacturing process by avoiding complex post-bonding operations and allowing parallel processing of multiple wafers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient three-dimensional integration of qubits with reduced loss tangent and preserved substrate properties, enhancing the performance of quantum information devices by allowing for both vertical and planar Josephson junctions within the same device.
Implementation Method 1
a first buried layer that can comprise a first patterned superconducting layer of a first wafer bonded to a second patterned superconducting layer of a second wafer
Implementation Method 2
The through-silicon via can be filled with a superconducting metal
Implementation Method 3
preserving the crystalline silicon substrate properties by pre-patterning the wafers to avoid etching through the entire structure, thus maintaining low loss tangent and coherence times
Implementation Method 4
allowing for the integration of qubits with both vertical and planar Josephson junctions
Data Source
AI summary
Techniques related to a three-dimensional integration for qubits on multiple height crystalline dielectric and method of fabricating the same are provided. A superconductor structure can comprise a first buried layer that can comprise a first patterned superconducting layer of a first wafer bonded to a second patterned superconducting layer of a second wafer. The superconductor structure can also comprise a patterned superconducting film attached to the second wafer. Further, the superconductor structure can comprise a second buried layer that can comprise a third patterned superconducting layer of a third wafer bonded to the patterned superconducting film that can be attached to the second wafer.