Computer-Bus Non-Posted Writes with Queue-Aware Status
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Solution Overview
Problem
The increasing complexity of computing systems and the demand for higher performance and power savings in different market segments, such as servers and mobile ecosystems, necessitate improved interconnect architectures that balance bandwidth and energy efficiency, particularly in heterogeneous computing environments where specialized processors like graphics processors and accelerators are used.
Innovation Solution
Implementing a multi-protocol link with Coherence Bias mechanisms that allow processors and accelerators to access memory using distinct protocol flows, optimizing for efficient accelerator access and host access, and incorporating shared virtual memory architectures to reduce cache coherence overheads and enhance energy efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If traditional cache coherence protocols are used in heterogeneous computing systems, then memory access consistency is maintained, but energy consumption increases and performance decreases due to coherence overheads
Solution Approach 1:
The patent segments memory access protocols into two distinct paths: a first protocol flow for host processors that maintains full cache coherence, and a second protocol flow for accelerators that bypasses cache coherence mechanisms. This segmentation allows each type of processor to use the appropriate protocol, reducing overall coherence overhead while maintaining consistency where required.
Solution Approach 2:
The patent applies different quality levels of cache coherence to different processor types. Host processors receive full coherence guarantees (higher quality), while accelerators operate with relaxed coherence (lower quality but sufficient for their workloads). This local quality differentiation reduces the burden of universal coherence protocols while maintaining necessary consistency.
2Productivity
If unified memory access protocols are used for both hosts and accelerators, then system simplicity is maintained, but performance efficiency decreases due to inability to optimize for specific access patterns
Solution Approach 1:
The patent introduces dynamic protocol selection where the memory access protocol is not fixed but adapts based on the type of processor making the request. The system dynamically chooses between first and second protocol flows based on whether the request originates from a host processor or an accelerator, enabling optimization without requiring complex static architecture design.
Solution Approach 2:
The patent introduces an intermediary component (such as a bridge or controller) that sits between processors and memory, intelligently routing requests through appropriate protocol flows. This intermediary handles the complexity of protocol selection and translation, allowing processors to use simple interfaces while the intermediary manages the sophisticated multi-protocol architecture.
3Loss of energy
If accelerators use standard memory access methods, then ease of implementation is maintained, but energy efficiency decreases due to unnecessary cache coherence overheads
Solution Approach 1:
The patent implements preliminary classification of memory requests at the point of origin, identifying whether a request comes from a host processor or an accelerator before the request enters the memory subsystem. This preliminary action allows the system to pre-select the appropriate protocol flow, preventing unnecessary coherence processing from the outset and reducing energy waste while maintaining clear implementation boundaries.
Data Source
AI summary
Systems and devices can include a controller and a command queue to buffer incoming write requests into the device. The controller can receive, from a client across a link, a non-posted write request (e.g., a deferred memory write (DMWr) request) in a transaction layer packet (TLP) to the command queue; determine that the command queue can accept the DMWr request; identify, from the TLP, a successful completion (SC) message that indicates that the DMWr request was accepted into the command queue; and transmit, to the client across the link, the SC message that indicates that the DMWr request was accepted into the command queue. The controller can receive a second DMWr request in a second TLP; determine that the command queue is full; and transmit a memory request retry status (MRS) message to be transmitted to the client in response to the command queue being full.