Queue Buffer De-queuing Arbitration for Fabric Switch Latency

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Solution Overview

Problem

Fabric switches experience transmission delays due to queuing of packets addressed to the same port, leading to reduced performance as they wait for complete packets before transmission can begin, resulting in increased latency and inefficiency.

Innovation Solution

A queue buffer arbitration system that prioritizes the de-queuing of packets based on completeness, using tail signals to identify complete packets and initiate transmission only when the entire packet is available, thereby reducing the likelihood of waiting for missing packet portions and minimizing delays.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If packets are queued at the output port, then multiple packets can be buffered for transmission, but transmission delays occur reducing fabric switch performance

Engineering Contradiction:
Improvenumber of buffered packetsVSAvoidtransmission delay
Core Design Contradiction:
Quantity of substanceVSLoss of time

Solution Approach 1:

The system performs preliminary validation of packet completeness before initiating transmission. The tail signal mechanism pre-checks whether a complete packet is available in the queue buffer before the arbitration process, preventing wasted arbitration cycles and reducing transmission delays by ensuring only complete packets are transmitted.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If the switch waits for complete packets before transmission, then data integrity is maintained, but latency increases

Engineering Contradiction:
Improvedata integrityVSAvoidlatency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The queue buffer provides feedback through tail signals to the arbiter, indicating when complete packets are available. This feedback mechanism allows the system to dynamically adjust transmission timing based on actual packet availability, maintaining data integrity while minimizing latency by transmitting complete packets as soon as they are ready.

Inventive Principle:
Principle #23Feedback

3Speed

If de-queuing is initiated before complete packet receipt, then transmission speed increases, but incomplete packets are transmitted causing errors

Engineering Contradiction:
Improvetransmission speedVSAvoidpacket completeness
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The system performs preliminary validation of packet completeness before initiating transmission. The tail signal mechanism pre-checks whether a complete packet is available in the queue buffer before the arbitration process, preventing wasted arbitration cycles and reducing transmission delays by ensuring only complete packets are transmitted.

Inventive Principle:
Principle #10Preliminary action

4Reliability

If arbitration waits for tail signals indicating complete packets, then complete packets are transmitted, but de-queuing delays increase

Engineering Contradiction:
Improvecomplete packet transmissionVSAvoidde-queuing delay
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The queue buffer provides feedback through tail signals to the arbiter, indicating when complete packets are available. This feedback mechanism allows the system to dynamically adjust transmission timing based on actual packet availability, maintaining data integrity while minimizing latency by transmitting complete packets as soon as they are ready.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS10419367B2Queue buffer de-queuing
Publication Date: 2019.09.17 HEWLETT PACKARD ENTERPRISE DEV LP
  • US10419367B2 patent drawing
  • US10419367B2 patent drawing
  • US10419367B2 patent drawing

AI summary

A method and apparatus determine which of a plurality of queue buffers (26, 126, 426) contains a complete packet and transmit a de-queue signal to one of the plurality of queue buffers (26, 126, 426) determined to contain a complete packet.