Submission Queue Buffer Resizing for Memory Sub-System Latency

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Solution Overview

Problem

Conventional memory sub-systems face challenges in maximizing bandwidth utilization and minimizing latency in highly threaded environments with variable queue depths, particularly in computing systems performing artificial neural network (ANN) and artificial intelligence (AI) tasks, due to unpredictable thread patterns and varying read sizes.

Innovation Solution

Implementing a dynamic prefetch mechanism in memory sub-systems with fast random access memory, using speculative prefetching and dynamic buffer allocation based on thread identification and read patterns to optimize data access.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If dynamic buffer allocation is implemented based on thread identification and read patterns, then bandwidth utilization is enhanced and latency is reduced, but device complexity increases

Engineering Contradiction:
Improvebandwidth utilizationVSAvoidbuffer management complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The buffer allocation strategy transitions from static to dynamic, where buffers are allocated and deallocated based on real-time thread activity and read patterns. The system monitors thread identification and read size variations to dynamically adjust buffer allocation, maximizing bandwidth utilization while adapting to changing workloads.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes buffer allocation parameters based on detected read patterns and thread characteristics. By monitoring read sizes and access patterns, the system adjusts buffer dimensions and allocation strategies to optimize performance for specific workload types, thereby enhancing bandwidth utilization without requiring overly complex fixed structures.

Inventive Principle:
Principle #35Parameter changes

2Loss of time

If dynamic buffer allocation is implemented based on thread identification and read patterns, then latency is reduced, but device complexity increases

Engineering Contradiction:
Improveaccess latencyVSAvoidbuffer management complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The system performs preliminary buffer allocation based on predicted read patterns before actual data access occurs. By analyzing historical read patterns and thread behavior, the system pre-allocates appropriate buffers, reducing access latency when threads actually need data without requiring complex real-time allocation decisions.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The buffer management system incorporates feedback mechanisms that monitor thread activity, read patterns, and access latency. This feedback is used to continuously refine buffer allocation strategies, reducing latency over time while keeping the management complexity manageable through iterative optimization rather than complex predetermined rules.

Inventive Principle:
Principle #23Feedback

3Productivity

If speculative prefetching is implemented, then bandwidth utilization is enhanced, but reliability may be affected due to unpredictable thread patterns

Engineering Contradiction:
Improvebandwidth utilizationVSAvoidprefetch accuracy
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The speculative prefetching mechanism applies local quality by tailoring prefetch strategies to specific threads and their individual access patterns. Rather than using a uniform prefetch approach, the system analyzes and adapts prefetching behavior to match each thread's unique read patterns, improving bandwidth utilization while maintaining reliability through pattern-specific optimization.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20260056680A1Dynamic Management of Buffers for Submission Queues in Communications between a Memory Sub-System and a Host System
Publication Date: 2026.02.26 MICRON TECHNOLOGY INC
  • US20260056680A1 patent drawing
  • US20260056680A1 patent drawing
  • US20260056680A1 patent drawing

AI summary

A method to facilitate communications between a memory sub-system and a host system, including: allocating, from a random access memory of the memory sub-system, a first buffer to buffer data to be used during execution of commands communicated to the memory sub-system via a first submission queue from the host system; retrieving, from the first submission queue, a command; determining a size of a data chunk used during execution of the command; determining a preferred size of the first buffer based on the size of the data chunk; determining whether to change the first buffer according to the preferred size; and changing the first buffer to the preferred size.