Queue-Latency Packet Buffering for On-Chip Buffer Utilization

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Solution Overview

Problem

Existing packet buffering methods fail to accurately distinguish between congested and non-congested packets, leading to inefficient utilization of on-chip buffers and potential discarding of non-congested packets due to insufficient bandwidth in external buffers.

Innovation Solution

A packet buffering method that utilizes queue latency as an indicator to determine congestion status, allocating packets to either on-chip or external buffers based on queue latency thresholds, ensuring non-congested packets are buffered in the on-chip buffer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If queue depth is used as the indicator for determining queue congestion status, then the congestion status can be monitored, but the congestion status cannot be accurately reflected leading to improper buffer allocation

Engineering Contradiction:
Improvecongestion status detection accuracyVSAvoidon-chip buffer utilization efficiency
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The patent changes the indicator parameter from queue depth to queue latency. Queue latency is calculated as the difference between the current time and the enqueue time of the oldest packet in the queue. This parameter change enables accurate identification of congested queues, allowing proper buffer allocation and improving on-chip buffer utilization efficiency.

Inventive Principle:
Principle #35Parameter changes

2Quantity of substance

If congested packets are buffered in the on-chip buffer, then the on-chip buffer capacity is utilized, but non-congested packets may be discarded due to insufficient external buffer bandwidth

Engineering Contradiction:
Improvepacket buffering capacityVSAvoidpacket delivery reliability
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent implements a feedback mechanism where queue latency is continuously monitored and used to identify congested queues. When a queue is identified as congested (queue latency exceeds threshold), incoming packets from that queue are directed to the external buffer. This feedback loop ensures that only truly congested packets occupy external buffer resources, preventing discarding of non-congested packets and improving packet delivery reliability.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent applies different buffer allocation strategies to different queues based on their congestion status. Congested queues (identified by high queue latency) are directed to the external buffer, while non-congested queues are served from the on-chip buffer. This local quality differentiation optimizes packet handling for each queue's specific conditions, improving overall system reliability.

Inventive Principle:
Principle #3Local quality

3Ease of operation

If non-congested packets are buffered in the external buffer, then the on-chip buffer is preserved for congested packets, but the limited bandwidth of the external buffer causes packet discarding

Engineering Contradiction:
Improvebuffer management simplicityVSAvoidpacket throughput
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

The system continuously monitors queue latency and provides feedback to the buffer allocation decision. When queue latency indicates congestion, packets are redirected to the external buffer. This feedback mechanism ensures that the external buffer is used only when necessary, maximizing packet throughput while maintaining simple buffer management operations.

Inventive Principle:
Principle #23Feedback

Data Source

PatentEP4072084B1Message buffering method, integrated circuit system, and storage medium
Publication Date: 2025.09.03 HUAWEI TECH CO LTD
  • EP4072084B1 patent drawingFigure 1
  • EP4072084B1 patent drawingFigure 2
  • EP4072084B1 patent drawingFigure 3

AI summary

This application relates to the field of data communication, and in particular, to a packet buffering method, an integrated circuit system, and a storage medium. The method can properly allocate an on-chip buffer and improve utilization of the on-chip buffer. The packet buffering method may be applied to a network device. The network device includes a first storage medium and a second storage medium. The first storage medium is inside a chip of a processor of the network device, and the second storage medium is outside the processor. The method may include: receiving a first packet, and identifying a queue number of the first packet, where the queue number indicates a queue for storing a buffer address of the first packet; querying a queue latency of the queue based on the queue number; querying usage of the first storage medium, and determining a first latency threshold based on the usage; and buffering the first packet in the first storage medium if the queue latency is less than the first latency threshold, or buffering the first packet in the second storage medium if the queue latency is greater than the first latency threshold.