Hardware Queue Manager for Multi-Processor Shared Memory

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Solution Overview

Problem

In multi-processor systems, managing shared memory access among multiple processors can lead to conflicts and overhead due to the need for processors to inspect queues and coordinate with each other, which complicates simultaneous operations.

Innovation Solution

A hardware queue manager is introduced to intercept messages, calculate addresses for available queue elements, and perform queuing operations dynamically, relieving processors from direct queue management and allowing simultaneous access without conflicts.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple processors directly access and manage queues in shared memory, then processors can perform simultaneous operations, but conflicts and coordination overhead occur

Engineering Contradiction:
Improveprocessing speedVSAvoidqueue management complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

A queue manager is introduced as an intermediary component between multiple processors and the shared memory queue. The queue manager intercepts queue access requests from processors, manages the actual queue operations, and returns results to processors. This mediator handles all queue management complexity, allowing processors to access queues simultaneously without direct coordination, thus resolving the contradiction between high productivity and low device complexity

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The queue management functionality is extracted from the processors themselves and placed into a dedicated queue manager component. Processors no longer need to inspect queues or coordinate access, as these functions are separated out and handled by the queue manager. This extraction eliminates the coordination overhead from processors while maintaining simultaneous access capability

Inventive Principle:
Principle #2Taking out (Extraction)

2Reliability

If processors inspect queues to avoid conflicts, then access safety is maintained, but overhead increases and performance decreases

Engineering Contradiction:
Improveaccess safetyVSAvoidcoordination time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The queue manager is designed to autonomously manage queue access without requiring processors to inspect or coordinate. The queue manager internally tracks queue state, handles conflicts, and ensures safe access. Processors simply issue requests to the queue manager, which self-manages the safety aspects, eliminating the time processors would spend on inspection and coordination while maintaining access safety

Inventive Principle:
Principle #25Self-service

3Productivity

If a hardware queue manager is introduced to manage queues, then processor overhead is reduced, but system complexity increases

Engineering Contradiction:
Improveprocessor efficiencyVSAvoidsystem architecture complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The queue manager is designed as a universal component that can serve multiple processors and potentially multiple queues simultaneously. By consolidating queue management functionality into a single multi-functional component, the system avoids duplicating queue management logic across multiple processors. This universality improves processor efficiency while the modular design of the queue manager keeps the added system complexity manageable and centralized

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS10210095B2Configurable hardware queue management and address translation
Publication Date: 2019.02.19 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US10210095B2 patent drawing
  • US10210095B2 patent drawing
  • US10210095B2 patent drawing

AI summary

A system for managing one or more queues in a multi-processor environment includes a shared memory configured to be accessed by a plurality of processing elements, and a queue manager configured to control a queue in the shared memory, the queue manager storing dynamically configurable queue parameters including an operation address associated with the queue, a number of queue elements and a size of each queue element. The queue manager is configured to intercept a message from a processing element, the message directed to the shared memory and specifying the operation address, calculate an address of a location in the shared memory corresponding to one or more available queue elements, the calculating performed based on the operation address, the number of queue elements, and the size of each queue element, and perform one or more queuing operations on the queue based on the calculated address.