Hardware Queue Manager Watermarking for Multi-Processor Overrun Prevention

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Solution Overview

Problem

In multi-processor systems, managing shared memory access among multiple processors can lead to conflicts and overruns due to the need for processors to inspect queues and coordinate access, which increases overhead and processing loads.

Innovation Solution

A dynamically configurable hardware queue manager intercepts messages from processors, performs queuing operations, and sets threshold values (watermarks) to prevent overruns by ensuring sufficient queue space, allowing processors to access shared memory without direct queue inspection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If processors directly inspect queues to manage shared memory access, then queue management precision is improved, but processing overhead increases and conflicts occur

Engineering Contradiction:
Improvequeue management precisionVSAvoidprocessing overhead
Core Design Contradiction:
Measurement precisionVSLoss of energy

Solution Approach 1:

The patent introduces a queue manager as an intermediary component between processors and queues. The queue manager intercepts enqueue operations from multiple processors, manages queue state, and prevents overruns without requiring processors to directly inspect queue status. This mediator approach resolves the contradiction by eliminating the need for processors to perform costly queue inspections while maintaining precise queue management through the dedicated queue manager component.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Speed

If multiple processors access shared memory simultaneously without coordination, then processing speed is improved, but conflicts and overruns occur

Engineering Contradiction:
Improveprocessing speedVSAvoidqueue overrun prevention
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The queue manager implements self-service mechanisms by automatically tracking queue full conditions through watermark thresholds. When the queue reaches the high watermark threshold, the queue manager autonomously prevents further enqueue operations without requiring processor intervention or coordination. This self-managing approach allows multiple processors to access shared memory simultaneously at high speed while the queue manager independently ensures reliability by preventing overruns.

Inventive Principle:
Principle #25Self-service

3Reliability

If processors communicate to avoid conflicts in queue access, then queue management reliability is improved, but processing overhead increases

Engineering Contradiction:
Improvequeue access coordinationVSAvoidprocessing overhead
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent extracts the coordination and communication functions from the processors themselves and concentrates them in a dedicated queue manager component. The queue manager centralizes the logic for detecting queue full conditions, managing watermarks, and preventing overruns. This extraction eliminates the need for processors to communicate with each other for queue coordination, thereby maintaining high reliability while significantly reducing processing overhead and inter-processor communication requirements.

Inventive Principle:
Principle #2Taking out (Extraction)

4Quantity of substance

If queue size is increased to accommodate multiple processors, then queue capacity is improved, but memory usage increases

Engineering Contradiction:
Improvequeue capacityVSAvoidmemory usage
Core Design Contradiction:
Quantity of substanceVSVolume of stationary object

Solution Approach 1:

The patent implements dynamic watermark thresholds (high watermark and low watermark) that adapt to the number of active processors and queue conditions. The high watermark threshold dynamically determines when the queue is full based on current system state, allowing the queue to efficiently utilize available memory without excessive allocation. This dynamic approach optimizes the balance between queue capacity and memory usage, accommodating multiple processors while preventing unnecessary memory consumption.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS10310996B2Hardware queue manager with water marking
Publication Date: 2019.06.04 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US10310996B2 patent drawing
  • US10310996B2 patent drawing
  • US10310996B2 patent drawing

AI summary

A system for managing one or more queues in a multi-processor environment includes a memory configured to be accessed by a plurality of processing elements, and a queue manager disposed in communication with a plurality of processors and with the memory, the queue manager configured to control a queue in the memory, the queue including a plurality of queue elements, the queue manager configured to intercept a message from a processing element of the plurality of processing elements and perform one or more queuing operations on the queue based on the message. The system also includes a dynamically configurable queue full value maintained by the queue manager, the queue full value being a threshold value that specifies a maximum number of the queue elements that can be written to before a queue full condition is detected, the maximum number based on a number of processing elements.