Queued SPI Interface Arbitration for Multi-Slave Management
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Solution Overview
Problem
The existing SPI communication interfaces face complexity in managing multiple slave devices due to the need for frequent re-configuration and lack of efficient queue management, leading to security issues, increased processing power, and memory usage when multiple software tasks share a single SPI interface.
Innovation Solution
A processing system with a queued serial peripheral interface (SPI) that includes multiple hardware SPI interfaces, each with a transmission and reception FIFO memory, an arbiter, and a control circuit, allowing for independent configuration and data exchange with each slave device, and utilizing DMA channels for efficient data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple software tasks share a single SPI interface, then resource utilization is improved, but security issues arise and processing complexity increases
Solution Approach 1:
The single SPI interface is segmented into multiple independent virtual interfaces, each assigned to a specific software task. Each virtual interface has its own configuration parameters and communication channels, allowing multiple tasks to operate independently without interfering with each other, thus maintaining security while improving resource utilization.
Solution Approach 2:
An intermediary management layer is introduced between the hardware SPI interface and multiple software tasks. This intermediary handles task scheduling, configuration management, and data routing, reducing the processing complexity for individual tasks while enabling secure multi-task access to the shared hardware interface.
2Adaptability or versatility
If frequent re-configuration is performed to manage multiple slave devices, then adaptability is improved, but processing power consumption increases
Solution Approach 1:
Configuration parameters for multiple slave devices are pre-loaded into a configuration memory before runtime. When a slave device needs to be accessed, the system retrieves pre-configured parameters instead of performing frequent re-configuration operations, significantly reducing processing power consumption while maintaining the ability to manage multiple slave devices adaptively.
3Device complexity
If a single SPI interface is used for multiple slave devices, then device complexity is reduced, but memory usage increases
Solution Approach 1:
A universal configuration memory structure is designed to store parameters for multiple slave devices in a standardized format. This universal structure allows the system to manage multiple slave devices through a single SPI interface while optimizing memory usage through efficient parameter storage and retrieval mechanisms, avoiding the need for separate memory allocations for each device.
Data Source
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AI summary
A processing system (10a) comprising a queued Serial Peripheral Interface, SPI, circuit (30a) is described. The SPI circuit (30a) comprises a hardware SPI communication interface (36), an arbiter (34) and a plurality of interface circuits (320..32n). Specifically, each interface circuit (320..32n) comprises a transmission FIFO memory (320), a reception FIFO memory (322) and an interface control circuit (324). The interface control circuit (324) is configured to receive one or more first data packets from a digital processing circuit (102) and store the received one or more first data packets to the transmission FIFO memory (320). Next, the interface control circuit (324) sequentially reads the one or more first data packets from the transmission FIFO memory (320), extracts from the one or more first data packets at least one transmission data word (DATA), and provides the at least one extracted transmission data word (DATA) to the arbiter (34). In turn, interface control circuit (324) receives from the arbiter (34) a reception data word (RXDATA) and stores one or more second data packets to the reception FIFO memory (322), the one or more second data packets comprising the received reception data word (RXDATA). Finally, the interface control circuit (324) sequentially reads the one or more second data packets from the reception FIFO memory (322) and transmits the one or more second data packets to the digital processing circuit (102).