Hardware Offload for QUIC Address Validation
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Solution Overview
Problem
QUIC servers are vulnerable to first-flight attacks during initial handshakes, which can lead to resource exhaustion, and existing address validation methods increase server latency and CPU utilization.
Innovation Solution
Offloading address validation from the software stack to hardware devices such as network interface devices, switches, or routers, which perform decoding, token generation, and validation, reducing CPU load and mitigating DDOS attacks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If address validation is performed by the software stack during QUIC connection establishment, then security against first-flight attacks is improved, but CPU utilization increases and latency increases
Solution Approach 1:
The patent introduces a hardware device as an intermediary between the network interface and the software stack. This hardware device performs address validation operations (decoding Client Initial Messages, generating retry tokens, validating tokens) that were previously handled by the CPU running the software stack. By offloading these security-critical operations to dedicated hardware, the CPU is freed from these tasks while the hardware independently performs validation to prevent first-flight attacks.
Solution Approach 2:
The patent extracts the address validation functionality from the software stack and implements it in hardware. Specifically, functions such as decoding Client Initial Messages, generating retry tokens, and validating tokens are removed from the software processing path and implemented as separate hardware operations. This extraction reduces the computational burden on the CPU while maintaining security functionality.
2Reliability
If address validation is performed by the software stack during QUIC connection establishment, then security against first-flight attacks is improved, but connection setup latency increases
Solution Approach 1:
The hardware device acts as an intermediary that performs address validation operations in parallel with or independent of the software stack processing. By implementing decoding, token generation, and validation in hardware, these operations can be executed more rapidly and without blocking the software processing path, thereby reducing the overall connection setup latency while maintaining security.
Solution Approach 2:
The patent replaces software-based address validation operations with hardware-based operations. Hardware circuits can perform decoding, token generation, and validation operations in parallel and with lower latency compared to software execution. This substitution of mechanical/software processes with hardware processes reduces connection setup time while maintaining security functionality.
3Productivity
If address validation is offloaded to hardware devices, then CPU utilization is reduced and security is improved, but device complexity increases
Solution Approach 1:
The patent segments the QUIC connection establishment process into distinct functional modules that can be independently implemented in hardware. The hardware device is divided into separate units for decoding Client Initial Messages, generating retry tokens, and validating tokens. This segmentation allows for modular hardware design, making the system more manageable and maintainable despite the increased complexity.
Solution Approach 2:
The hardware device is designed to perform multiple functions related to address validation: decoding Client Initial Messages, generating retry tokens, and validating tokens. By consolidating these related functions into a single multi-functional hardware unit, the patent reduces overall system complexity compared to having separate hardware components for each function, while still achieving CPU offloading and security improvements.
Data Source
AI summary
Examples described herein relate to an interface and circuitry. The circuitry can perform offloaded performance of a cryptographic handshake with a client in connection with initiation of a quick User Datagram Protocol Internet Connections (QUIC) connection with the client. In some examples, the cryptographic handshake comprises process a first client hello datagram from the client, the first client hello datagram is consistent with QUIC, and the offloaded performance of the cryptographic handshake with the client is offloaded from a processor to the circuitry.