Modified QUIC Protocol Hardware Offloading via Fixed Field Parsing
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Solution Overview
Problem
The QUIC protocol is computationally intensive and challenging for hardware implementation due to its variable-length fields, complex frame structures, and lack of a specific frame order, making it inefficient for hardware offloading and resource consumption.
Innovation Solution
A modified QUIC protocol (OQUIC) with fixed field sizes and a predefined frame-type order is introduced, allowing for efficient hardware offloading by reducing computational intensity and eliminating the need for complex iterative parsing and per-connection state management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the conventional QUIC protocol is implemented in software to provide high security and enhanced recovery, then security and reliability are improved, but CPU utilization increases and resource consumption rises
Solution Approach 1:
The patent replaces software-based QUIC protocol processing with a hardware implementation (network processor or ASIC) that can parse and process QUIC packets at line rate without consuming CPU resources. The hardware parser uses fixed field sizes and predefined frame-type orders to enable efficient hardware-friendly processing, substituting the mechanical software processing with dedicated hardware circuitry.
2Adaptability or versatility
If the QUIC protocol uses variable-length fields and complex frame structures to provide flexibility, then adaptability is improved, but device complexity increases and hardware implementation becomes challenging
Solution Approach 1:
The patent changes the parameters of the QUIC protocol by introducing fixed field sizes (e.g., fixed connection ID length, fixed frame header lengths) and predefined frame-type orders. These parameter changes simplify the protocol structure to be hardware-friendly while maintaining the essential functionality, allowing hardware parsers to process packets efficiently without complex iterative parsing.
3Measurement precision
If the QUIC protocol requires complex iterative parsing to process variable-length fields, then measurement precision is improved, but processing speed decreases and productivity is reduced
Solution Approach 1:
The patent applies preliminary action by pre-defining field sizes and frame-type orders in the protocol specification. This allows hardware parsers to process packets using simple, fixed-width field extraction and predefined parsing sequences, eliminating the need for complex iterative parsing during runtime. The parsing structure is prepared in advance to enable high-speed hardware processing.
Data Source
AI summary
A data transmission controller is configured to generate one or more data transmission packets according to the modified QUIC protocol by generating one or more fields in the one or more data transmission packets to have a fixed field-size and generating a predefined number of frames of different frame-types in a predefined frame-type order in the one or more data transmission packets. The data transmission controller enables hardware Offload variant of the QUIC protocol for efficient hardware implementations of the modified QUIC protocol.