QUIC Packet Processing Hardware Offloads for Lower CPU Usage
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Solution Overview
Problem
Current QUIC protocol implementations are fully software-based, leading to inefficient processing and high processor usage, which is a bottleneck for improved throughput and latency reduction.
Innovation Solution
Implementing hardware accelerators for QUIC packet processing, including cryptographic and receive-side scaling, to segment and encrypt large packets, and distribute processing across multiple processor cores.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If hardware accelerators are implemented for QUIC packet processing, then throughput is improved and processor usage is reduced, but device complexity increases
Solution Approach 1:
A network controller is introduced as an intermediary component between the processor and the QUIC packet processing function. The network controller hardware accelerator performs cryptographic operations and packet segmentation offloaded from the processor, thereby improving throughput while containing the complexity increase to a dedicated hardware module rather than the main processor architecture
Solution Approach 2:
The patent replaces software-based QUIC packet processing with a hardware accelerator that uses dedicated circuitry for cryptographic operations and packet handling. This substitution of mechanical/software processing with hardware-based processing significantly improves throughput and reduces processor usage for these specific functions
2Device complexity
If QUIC packet processing is performed entirely in software, then device complexity is lower, but processor usage is high and throughput is limited
Solution Approach 1:
The patent extracts the QUIC packet processing function from the general-purpose processor and implements it as a dedicated network controller hardware accelerator. This extraction removes the processing burden from the processor, reducing its usage for these functions while maintaining lower overall system complexity through modular architecture
Solution Approach 2:
The network controller is segmented into functional units including a processor portion for control logic and a hardware accelerator portion for cryptographic operations. This segmentation allows the complex processing function to be divided into manageable components that can be optimized independently
Data Source
AI summary
Technologies for accelerated QUIC packet processing include a computing device having a network controller. The computing device programs the network controller with an encryption key associated with a QUIC protocol connection. The computing device may pass a QUIC packet to the network controller, which encrypts a payload of the QUIC packet using the encryption key. The network controller may segment the QUIC packet into multiple segmented QUIC packets before encryption. The network controller transmits encrypted QUIC packets to a remote host. The network controller may receive encrypted QUIC packets from a remote host. The network controller decrypts the encrypted payload of received QUIC packets and may evaluate an assignment function with an entropy source in the received QUIC packets and forward the received QUIC packets to a receive queue based on the assignment function. Each receive queue may be associated with a processor core. Other embodiments are described and claimed.