QUIC Packet Offloading via Hardware Encryption
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Solution Overview
Problem
Current QUIC implementations in software do not support hardware offloads, leading to bottlenecks in cryptographic and UDP processing, resulting in higher costs compared to supporting legacy protocols like TCP.
Innovation Solution
Offloading QUIC packet encryption and segmentation processing to dedicated hardware, such as FPGAs or ASICs, with minimal changes to host software, allowing the QUIC software stack to communicate with offloader hardware and optimize QUIC operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If QUIC is implemented in software only, then flexibility and adaptability are maintained, but processing performance deteriorates and costs increase
Solution Approach 1:
The patent segments QUIC processing into two parts: cryptographic operations (encryption/decryption) are offloaded to hardware, while protocol stack processing remains in software. This segmentation allows performance-critical functions to run in hardware while maintaining flexibility in software, resolving the contradiction between performance and complexity.
Solution Approach 2:
The patent introduces an intermediary interface layer between the QUIC software stack and hardware offload engine. This intermediary handles packet classification, metadata extraction, and coordination, allowing software to control hardware operations without direct hardware complexity exposure, thus improving performance while managing complexity.
2Speed
If hardware offload is implemented, then processing speed improves, but device complexity and deployment difficulty increase
Solution Approach 1:
The patent designs the hardware offload engine with a universal interface that can work with multiple QUIC connections and configurations through a single standardized architecture. This multi-functionality allows the same hardware design to serve various deployment scenarios, improving speed while simplifying deployment by avoiding custom hardware for each case.
Solution Approach 2:
The patent uses packet metadata copies and descriptors to pass information between software and hardware without requiring complex direct memory access or shared memory structures. This copying approach simplifies the interface design and deployment while maintaining high processing speed through efficient data transfer.
3Use of energy by moving object
If cryptographic processing is done in software, then implementation flexibility is maintained, but processor usage and costs increase
Solution Approach 1:
The patent extracts cryptographic processing functions from the general-purpose processor and places them in dedicated hardware. This extraction reduces processor usage for crypto operations while the hardware complexity is contained in a specialized component with a simple standardized interface, resolving the contradiction between energy efficiency and overall system complexity.
Data Source
AI summary
Embodiments include a method of opening a Quick User Datagram Protocol (UDP) Internet Connections (QUIC) socket on a computing platform, initializing QUIC packet processing of a hardware-based offloader, opening a QUIC connection to the offloader, and transmitting a first QUIC packet to the offloader over the QUIC connection. The hardware-based offloader encrypts and transmits the QUIC packet.