Receiving Apparatus Offloads QUIC Decryption from CPU
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Solution Overview
Problem
Current communication apparatuses that support the QUIC protocol face increased CPU utilization and memory constraints due to decrypting segment data packets using a central processing unit and storing headers in system memory, leading to inefficient resource usage.
Innovation Solution
A receiving apparatus with a packet parser, data memory, decrypt engine, transmission engine, header processing unit, and controller that preprocesses segment data packets by fetching and storing header information, selectively decrypting encrypted data to obtain QUIC private headers and payloads, and updating headers to generate packet information, thereby reducing CPU workload and optimizing memory usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the central processing unit decrypts each segment data packet, then the decryption function is achieved, but the utilization rate of the central processing unit increases
Solution Approach 1:
The patent segments the packet processing function into a dedicated receiving apparatus separate from the main CPU. The receiving apparatus includes specialized components (packet parser, decrypt engine, header processing unit) that handle QUIC packet decryption and processing independently, freeing the CPU from these repetitive tasks and reducing its utilization rate while maintaining reliable decryption functionality.
Solution Approach 2:
The receiving apparatus acts as an intermediary between the network interface and the CPU. It intercepts segment data packets, performs decryption and header processing, and prepares data for CPU processing only when necessary. This intermediary layer offloads routine decryption operations from the CPU, reducing its workload and utilization rate.
2Quantity of substance
If the system memory stores the header of the segment data packet, then the header storage is achieved, but the system memory cannot store other data
Solution Approach 1:
The patent extracts header storage functionality from the system memory by providing a dedicated data memory within the receiving apparatus. Headers of segment data packets are stored in this separate data memory, freeing system memory capacity for other data storage needs while ensuring headers are readily accessible for processing operations.
Solution Approach 2:
The patent introduces a new storage dimension by adding a separate data memory component within the receiving apparatus. This creates a hierarchical memory structure where headers are stored in the data memory (close to processing units) while payload data uses system memory, enabling both efficient header access and adequate system memory capacity for other purposes.
Data Source
AI summary
The present disclosure provides a receiving apparatus for preprocessing at least one segment data packet to a data packet. The receiving apparatus includes a packet parser, a data memory, a decrypt engine, a transmission engine, a header processing unit and a controller. The packet parser fetches segment-packet-header information from a segment packet header of each segment data packet. The decrypt engine decrypts an encrypted data of each segment data packet to obtain a segment payload and a QUIC private header including sequence information. The transmission engine transmits the segment payload to a specific location of a system memory. The header processing unit calculates packet information and updates the segment packet header stored in the data memory to generate a packet header. The controller controls the transmission engine based on the sequence information to output the packet header to the system memory for generating the data packet.