Quick Write Mechanism for Emulated EEPROM Data Integrity
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Solution Overview
Problem
Emulated electrically erasable (EEE) memory systems face challenges in quickly writing data to non-volatile memory before power loss, as conventional multiple program steps consume significant time, leading to potential data loss in automotive applications where power loss is imminent.
Innovation Solution
Implementing a quick write mechanism in the memory controller with quick write logic that bypasses conventional program steps like record qualification and compression during power loss, allowing for rapid creation and verification of quick records in non-volatile memory, which are later qualified and compressed when power is restored.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional multiple program steps are used to write data to non-volatile memory, then data integrity and reliability are improved, but write speed deteriorates causing data loss during imminent power loss
Solution Approach 1:
The patent implements a quick write mode that performs preliminary writing of data to non-volatile memory without executing the full sequence of conventional program steps (such as verification and compression). This preliminary action allows data to be written rapidly during imminent power loss conditions, sacrificing some integrity checks for speed. After power restoration, the previously skipped verification and compression steps are completed to ensure data integrity, thus resolving the contradiction between write speed and data integrity.
2Reliability
If all conventional program steps including verification and compression are executed, then data reliability is improved, but the time available to write data before power loss deteriorates
Solution Approach 1:
The patent segments the conventional multi-step write process into two distinct phases: a quick write phase that executes only essential write operations without verification or compression, and a post-power-restoration phase that completes the verification and compression steps. This segmentation allows the system to prioritize speed during power loss events by executing only the critical write operation, while deferring time-consuming reliability checks to after power restoration, thus resolving the contradiction between data reliability and time available before power loss.
3Speed
If quick write mode bypasses verification steps, then write speed is improved, but manufacturing precision of data writing deteriorates
Solution Approach 1:
The quick write mode performs a preliminary write of data to non-volatile memory without executing verification steps, achieving rapid data transfer. After power restoration, the system completes the previously skipped verification and compression operations to ensure data writing precision. This two-stage approach resolves the contradiction by performing speed-critical operations first, then precision-critical operations afterward, when time constraints are removed.
Data Source
AI summary
An embodiment for operation of an emulated electrically erasable (EEE) memory system includes a memory controller configured to identify a first quick record of a stack of quick records as a present record, wherein the stack of quick records are stored in a non-volatile portion of memory, the first quick record has a quick record status identifier (ID) that indicates the stack of quick records has not been qualified, determine a record status of a next record after the present record in the non-volatile portion of memory, and in response to a determination that the next record has a blank record status ID: update the next record from the blank record status ID to the quick record status ID, wherein the blank record status ID indicates that the next record is part of the stack of quick records, and qualify the present record using the plurality of program steps.