Quiescent State Retention Mode for Processor Power Management
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Solution Overview
Problem
Existing low power modes in electronic devices only moderately reduce power consumption, introduce unacceptable latencies, and can cause system instability upon re-entry to a running mode.
Innovation Solution
The implementation of a quiescent state retention mode (QSRM) that allows electronic devices to enter a new low power mode, utilizing a processor capable of discrete clock gating and an onboard or external power management integrated circuit (PMIC), which transitions between run, low power, and off states, enabling quick and stable resume of operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the processor is placed into sleep mode to reduce power consumption, then power savings are achieved, but unacceptable latencies are introduced to command execution
Solution Approach 1:
The system dynamically transitions between three distinct power states (run mode, low power mode, and quiescent state) rather than using a static sleep mode. This allows the processor to adapt its power consumption level based on operational requirements, achieving both power savings and rapid resumption by maintaining a middle ground low power state that can quickly transition to full operation.
Solution Approach 2:
The invention changes the power state parameters by introducing a quiescent state with specific characteristics (retained memory contents, disabled clocks, maintained voltage) that differ from traditional sleep modes. This parameter change enables the system to achieve lower power consumption while preserving the ability to rapidly resume operations without full wake-up sequences.
2Use of energy by moving object
If the processor enters sleep mode to save power, then energy consumption is reduced, but system instability occurs upon re-entry to running mode
Solution Approach 1:
The system prepares for potential instability by retaining memory contents and maintaining voltage levels during the quiescent state, creating a cushion against system instability. This pre-prepared state ensures that when transitioning back to run mode, the system can resume operations immediately without the instability issues that plague traditional sleep mode wake-ups.
Solution Approach 2:
The invention extracts the essential elements needed for stable operation (memory contents, voltage, peripheral device states) and preserves them during the quiescent state, separating these critical stability factors from the power-consuming clock signals. This extraction allows the system to achieve power savings while maintaining the core elements necessary for stable operation.
3Loss of time
If the processor remains in run mode to maintain responsiveness, then command execution latency is minimized, but significant power is consumed and heat is dissipated
Solution Approach 1:
The system employs periodic transitions between run mode and quiescent state, using wait-for-interrupt instructions to periodically check for events while in low power mode. This periodic action allows the processor to remain responsive to interrupts while spending most time in the power-saving quiescent state, achieving both low power consumption and maintained responsiveness.
Solution Approach 2:
The invention segments the processor operation into distinct phases (run mode, low power mode with wait-for-interrupt, and quiescent state), allowing different portions of time to be spent in different power states based on operational needs. This segmentation enables the system to achieve overall power savings while maintaining responsiveness during critical periods.
Data Source
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AI summary
A quiescent state retention mode (QSRM) permits minimal power consumption and dissipation by an electronic device while idle without producing adverse latencies to users or causing system instability. Upon a call to enter the QSRM, processes may be frozen, clocks may be gated, switching regulators may be placed in low power mode, SDRAM may be placed into self-refresh mode, caches may be flushed, IRQs may be disabled, and the system waits for interrupt to wakeup. In the QSRM, powered components include the switching regulator configured to provide power to the processor is maintained in a low power mode while the SDRAM is placed in self-refresh.