Quilt Package Nodule Interconnect for Microchip Integration

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Current microchip packaging technologies, such as Quilt Packaging, face limitations in further increasing integration and functionality without sacrificing performance or increasing costs, particularly in efficiently connecting multiple microchips and providing stable mechanical and electrical connections.

Innovation Solution

The development of an integrated circuit packaging system utilizing quilt package nodules on microchips for direct electrical and mechanical connections, including wirebonds and circuit elements, to connect multiple microchips via a substrate, enabling flexible configurations such as parallel, series, and series-parallel connections, and accommodating various microchip shapes and sizes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If Quilt Packaging with interconnect nodules is used to directly connect microchips, then device integration and functionality are improved, but mechanical stability and electrical connection reliability may be compromised

Engineering Contradiction:

Improveintegration and functionalityVSAvoidmechanical stability and electrical connection reliability

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

The interconnect structure is divided into multiple functional segments: a nodule portion formed on the microchip surface, a protruding portion that extends outward, and a receptacle structure with a cavity to receive the protruding portion. This segmentation allows each part to be optimized independently for its specific function while maintaining overall reliability.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The protruding portion of one interconnect nodule is inserted into and nested within the cavity of a receptacle structure on another microchip. This nesting arrangement creates a secure mechanical interlock while maintaining electrical connectivity, resolving the contradiction between integration and reliability.

Inventive Principle:

Principle #7Nested doll (Nesting)

2Device complexity

If interconnect nodules protrude over the edge of microchips to enable direct connections, then device complexity is reduced, but manufacturing precision requirements increase

Engineering Contradiction:

Improvepackaging complexityVSAvoidalignment precision of interconnect nodules

Core Design Contradiction:

Device complexityVSManufacturing precision

Solution Approach 1:

The protruding portions and receptacle structures are pre-formed on the microchips during the chip fabrication process using photolithography, etching, and plating techniques. This preliminary action ensures precise dimensional control and positioning before the chips are assembled, reducing the precision demands on the final assembly process.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The receptacle cavity acts as an intermediary structure that accommodates the protruding portion with built-in alignment tolerance. This intermediary design absorbs manufacturing variations and ensures reliable connection even with moderate precision, reducing the overall manufacturing precision requirements.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS10325875B2Edge interconnect packaging of integrated circuits for power systems

Publication Date: 2019.06.18 INDIANA INTEGRATED CIRCUITS LLC

AI summary

Disclosed is an integrated circuit packaging system that includes first and second microchips. Each microchip includes a top surface, a surface, one or more quilt package nodules fabricated on said top surface, and one or more bottom surface connectors. The system also includes a substrate to which the first and second microchips are mounted. The first and second microchips are connected via the quilt package nodules.