QV Memory Stack with Back-Channel DMA for Lower-Latency Access
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Solution Overview
Problem
Conventional RAM technologies face limitations in density, power dissipation, and data transfer bottlenecks, with persistent memory devices offering higher density but significant latency and system complexity, necessitating separate channels and controllers, which diminish their advantages.
Innovation Solution
A quasi-volatile memory (QV) stack with integrated memory controller on a separate die, using copper interconnects and TSVs, enables direct data transfers and shared control logic across multiple memory arrays, reducing power consumption and latency through internal DMA and error correction within the memory controller.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If persistent memory devices are used to achieve higher density, then storage capacity is improved, but latency and system complexity increase due to requiring separate channels and controllers
Solution Approach 1:
The patent combines persistent memory arrays with volatile memory arrays into a single unified memory device, eliminating the need for separate memory devices and their associated controllers. This integration allows the memory device to function as both volatile and non-volatile memory through the same physical infrastructure, reducing system complexity while maintaining high storage capacity.
Solution Approach 2:
The memory device is designed to serve multiple functions simultaneously - it operates as both volatile memory (for fast access) and non-volatile memory (for persistent storage) through the same device interface and control logic. This multi-functionality eliminates the need for separate channels and controllers that would otherwise be required for persistent memory devices.
2Speed
If conventional RAM technologies are used to achieve fast access speeds, then data access speed is improved, but density and power dissipation are limited
Solution Approach 1:
The patent utilizes phase-change material properties that can be switched between amorphous and crystalline states, enabling the memory to achieve both fast access speeds (comparable to volatile memory) and high density (comparable to persistent memory). The phase-change mechanism allows rapid data writing through localized heating and cooling cycles.
3Speed
If conventional RAM technologies are used to achieve fast access speeds, then data access speed is improved, but power dissipation increases
Solution Approach 1:
The memory employs periodic refresh operations for volatile memory regions rather than continuous power consumption. The phase-change memory cells maintain their state without power, and only require energy during write operations and periodic refreshes, significantly reducing overall power dissipation while maintaining fast access speeds.
Data Source
AI summary
A quasi-volatile memory (QV memory) stack includes at least one semiconductor die, having formed thereon QV memory circuits, bonded to a second semiconductor on which a memory controller for the QV memory (“QV memory controller”) is formed. The circuits in the bonded semiconductor dies are electrically connected using numerous copper interconnect conductors and conductive through-silicon vias (TSVs). The QV memory controller may include one or more interfaces to additional devices (“back-channel devices”) to enable the QV memory controller to also serve as a controller for each back-channel device and to provide additional services. The QV memory controller performs data transfers between a back-channel device and the QV memory without intervention by the host CPU.