3D Quasi-Volatile Memory Stack With Back-Channel Data Transfer
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Solution Overview
Problem
Current computer systems face challenges in achieving high performance due to limitations in memory speeds and power dissipation, with conventional DRAM reaching technology limits and persistent memory devices being slower than DRAM.
Innovation Solution
The implementation of a quasi-volatile memory (QV memory) stack, which includes semiconductor dies with QV memory circuits bonded to a memory controller die, using copper interconnects and through-silicon vias (TSVs), allowing for direct data transfers between QV memory and back-channel devices without CPU intervention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional DRAM is used for high-speed memory, then data access speed is improved, but power dissipation increases and technology limits are reached
Solution Approach 1:
The patent transitions from volatile DRAM to quasi-volatile memory by changing the fundamental operational parameters - using through-silicon via (TSV) technology to alter the electrical connection geometry, implementing new memory cell architectures that retain data longer, and modifying the refresh mechanisms to reduce power consumption while maintaining acceptable access speeds
Solution Approach 2:
The patent introduces a new dimension to memory architecture by stacking multiple memory layers vertically using TSV technology, moving from planar 2D DRAM structures to 3D stacked configurations. This dimensional change enables higher density and improved power efficiency without sacrificing access speed, as data can be accessed from multiple layers simultaneously
2Use of energy by moving object
If persistent memory devices are used to reduce power dissipation, then power consumption is reduced, but data access speed becomes slower
Solution Approach 1:
The patent segments the memory system into multiple functional layers - volatile memory layers for fast access and quasi-volatile layers for power-efficient storage - allowing the system to dynamically select or switch between modes based on access patterns, thereby achieving both speed and power efficiency
Solution Approach 2:
The quasi-volatile memory device serves multiple functions: it operates as high-speed memory when powered, provides non-volatile storage when power is removed, and can function in hybrid modes. This multi-functionality allows a single device to replace both DRAM and persistent memory, eliminating the speed penalty associated with dedicated persistent memory devices
3Device complexity
If CPU intervention is required for data transfers, then data transfer control is simplified, but system performance and efficiency decrease
Solution Approach 1:
The patent implements self-service capabilities in the memory controller, enabling automatic data transfers between the quasi-volatile memory and back-channel devices without CPU intervention. The controller autonomously manages data movement, error correction, and protocol handling, freeing the CPU for computational tasks and improving overall system performance
Data Source
AI summary
A quasi-volatile memory (QV memory) stack includes at least one semiconductor die, having formed thereon QV memory circuits, bonded to a second semiconductor on which a memory controller for the QV memory (“QV memory controller”) is formed. The circuits in the bonded semiconductor dies are electrically connected using numerous copper interconnect conductors and conductive through-silicon vias (TSVs). The QV memory controller may include one or more interfaces to additional devices (“back-channel devices”) to enable the QV memory controller to also serve as a controller for each back-channel device and to provide additional services. The QV memory controller performs data transfers between a back-channel device and the QV memory without intervention by the host CPU.