R-2R DAC Gate-Voltage Control for Switch Resistance Linearity

The patent applies different gate voltage control strategies to PMOS and NMOS switches based on their distinct electrical characteristics. Specifically, the gate voltage of PMOS switches is controlled to be higher than that of NMOS switches, compensating for the inherently higher ON resistance of PMOS devices. This localized differentiation in control parameters resolves the contradiction by maintaining CMOS compatibility while achieving balanced ON resistances and high output accuracy.

The patent dynamically adjusts the gate voltage parameters of PMOS and NMOS switches to compensate for resistance mismatches. By varying the gate voltage levels according to the specific bit position and switch type, the system achieves equalized ON resistances without requiring physical modification of the switches. This parameter-based compensation resolves the accuracy issue while maintaining standard CMOS fabrication processes.

The patent employs a universal gate voltage control mechanism that serves multiple functions: it equalizes ON resistances across different switch types, provides linearity correction for various bit positions, and operates within the existing single-rail CMOS supply structure. This multi-functional approach achieves high output accuracy without requiring additional supply rails or external trimming circuits, thereby resolving the contradiction between accuracy and device complexity.

The system uses internally generated control voltages derived from the existing reference voltage to automatically compensate for resistance mismatches. The gate voltage control circuitry is integrated within the DAC itself, using the available voltage references to generate the appropriate gate drive signals. This self-service mechanism eliminates the need for external trimming circuits or additional supply rails while maintaining high output accuracy.

The patent employs dynamic gate voltage adjustment where the control voltage applied to MOS switches varies depending on the bit position and switch type. For higher significance bits, the gate voltage is optimized to maintain linearity, while for lower significance bits, the control focuses on matching ON resistances. This dynamic adaptation resolves the contradiction by allowing the system to optimize for linearity where needed and for resistance matching where needed, without being constrained by fixed Vds requirements.

The patent applies differentiated gate voltage control strategies to different parts of the resistor ladder based on bit significance. Higher significance bits use control parameters optimized for linearity, while lower significance bits use parameters optimized for resistance matching. This localized quality approach allows the system to achieve both low sensitivity to mismatches and high linearity in different regions of the DAC without compromise.