R2R DAC Switch Voltage Regulation for Low Non-Linearity
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Solution Overview
Problem
Existing R2R resistor ladder DACs suffer from non-linearity due to differences in on-resistance (RON) between high-side and low-side switches, leading to differential and integral non-linearity errors, which are exacerbated in high-resolution DACs.
Innovation Solution
A voltage regulator is used to regulate the gate voltages of PFET and NFET switches, ensuring matched RON values by employing a differential amplifier and resistor networks to equalize the drain-source voltages of MOSFETs, thereby reducing non-linearity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If standard R2R resistor ladder DAC architecture is used, then high bit-precision can be achieved, but non-linearity errors occur due to differences in on-resistance between high-side and low-side switches
Solution Approach 1:
The patent changes the gate voltage parameter of the switches to regulate and equalize their on-resistance values. By applying different gate voltages to high-side and low-side switches, the patent compensates for inherent resistance differences, thereby reducing non-linearity errors while maintaining high bit-precision in the DAC output
Solution Approach 2:
The patent implements a feedback mechanism where the gate voltage is adjusted based on the actual on-resistance values of the switches. This feedback loop continuously monitors and corrects resistance mismatches, ensuring that the DAC maintains high precision without suffering from non-linearity errors caused by switch resistance variations
2Manufacturing precision
If larger switches are used to reduce on-resistance differences, then non-linearity is reduced, but device area increases
Solution Approach 1:
Instead of increasing switch size to reduce resistance differences, the patent changes the electrical parameter (gate voltage) to achieve resistance equalization. This allows smaller switches to be used while still maintaining matched on-resistance values, thereby reducing non-linearity without increasing device area
Solution Approach 2:
The patent moves from a spatial solution (larger switches) to an electrical solution (gate voltage control). By operating in the electrical parameter dimension rather than the physical size dimension, the patent achieves resistance matching without the area penalty that would result from using larger switches
3Manufacturing precision
If gate voltages are regulated to equalize on-resistance, then non-linearity errors are reduced, but circuit complexity increases
Solution Approach 1:
The patent regulates gate voltage parameters to equalize on-resistance values, directly addressing non-linearity errors. This parameter control approach provides a systematic method for reducing precision errors while adding controlled complexity through voltage regulation circuits
Solution Approach 2:
The gate voltage regulation circuit serves multiple functions: it equalizes on-resistance values, reduces non-linearity errors, and maintains compatibility with the existing R2R ladder architecture. This multi-functionality justifies the added circuit complexity by providing comprehensive error correction without requiring separate correction circuits
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces non-linearity errors, allowing for the use of smaller switches while maintaining accuracy, particularly in high-resolution DACs.
Implementation Method 1
The voltage regulator includes a differential amplifier, a p-ladder that includes N cascade-connected PFETS
Implementation Method 2
an n-ladder that includes y×N cascade-coupled NFETS and has first and second ends
Data Source
AI summary
In described examples, an R2R digital-to-analog converter includes multiple arms and a voltage regulator. Respective arms include an arm switch with a p-channel MOSFET (PFET) switch and an n-channel MOSFET (NFET) switch. The voltage regulator includes a differential amplifier, a p-ladder that includes N cascade-coupled PFETS and has first and second ends, an n-ladder that includes y×N cascade-coupled NFETS and has first and second ends, a first resistor (resistance R), and a second resistor (resistance y×R). The first p-ladder end is coupled to a first terminal of the first resistor. The second terminal of the first resistor is coupled to an input of the differential amplifier and a first terminal of the second resistor. A second terminal of the second resistor is coupled to the first n-ladder end. An output of the differential amplifier is coupled to the second n-ladder end and provides a gate voltage of the NFET switch.