R-2R Interrupt Aggregation for Low-Pin, Low-Latency ICs
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Solution Overview
Problem
Current integrated circuit signaling architectures face challenges in reducing interrupt latency and pin count while efficiently processing interrupts from multiple peripheral devices, with existing solutions either increasing latency or consuming substantial power and resources.
Innovation Solution
An R-2R resistor ladder network is used to aggregate interrupts from peripheral devices, where each device is represented by a binary interrupt bit, and an analog-to-digital converter digitizes the voltage signal to identify interrupting devices, allowing for reduced pin count and low latency processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a direct GPIO architecture is used with a unique GPIO pin for each peripheral device, then interrupt processing latency is reduced, but the pin count increases
Solution Approach 1:
Multiple peripheral device interrupt signals are merged into a single aggregated interrupt signal line. The interrupt aggregator combines N peripheral interrupt inputs into one output that connects to the processor, reducing the number of GPIO pins from N to 1 while maintaining interrupt processing capability
Solution Approach 2:
An interrupt aggregator circuit is introduced as an intermediary component between peripheral devices and the processor. This aggregator resolves multiple interrupt signals into a single aggregated signal and provides interrupt identification information to the processor, eliminating the need for multiple direct GPIO connections
2Quantity of substance
If interrupts from multiple peripheral devices are aggregated onto a common pin in an open-drain embodiment, then the pin count is reduced, but interrupt processing latency increases due to polling
Solution Approach 1:
The interrupt aggregator provides feedback information to the processor about which specific peripheral device generated the interrupt. By analyzing the voltage levels on the R-2R ladder network, the aggregator identifies the interrupting device and communicates this information to the processor, eliminating the need for polling and enabling immediate interrupt response
Solution Approach 2:
The polling mechanism is replaced with an electrical measurement system using an R-2R resistor ladder network and voltage measurement. The system substitutes mechanical/electronic polling with direct voltage-level-based interrupt identification, achieving both low pin count and low latency
3Quantity of substance
If a row-column matrix approach is used to reduce pin count, then the number of GPIO pins is reduced, but the processing complexity and power consumption increase
Solution Approach 1:
The complex processing logic is extracted from the processor and implemented in the interrupt aggregator circuit. The aggregator performs the identification of interrupting devices through simple voltage level detection on the R-2R ladder, removing complex processing requirements from the main processor and reducing overall system complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables efficient identification and processing of interrupts from multiple peripheral devices with reduced latency and power consumption, using only two pins at the host integrated circuit, while uniquely identifying each interrupting device.
Implementation Method 1
An R-2R resistor ladder is provided having a plurality of rungs. Each peripheral device couples to the R-2R resistor ladder through its corresponding rung
Implementation Method 2
an analog-to-digital converter digitizes the voltage signal to identify interrupting devices
Data Source
Figure 1A
Figure 1B
Figure 2
AI summary
A host integrated circuit is provided with an interrupt aggregator having a signal terminal for coupling to the signal end of an R-2R resistor ladder that has a plurality of rungs corresponding to a plurality of peripheral devices. The interrupt aggregator is configured to process a voltage signal received at the signal terminal to identify any of the peripheral device that intend to trigger an interrupt to a processor.