Interpolation DAC Circuit Using R-2R and Resistor Ladder Segmentation
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Solution Overview
Problem
Conventional digital-to-analog converter (DAC) circuits for microcontrollers face challenges in achieving high accuracy (e.g., 16-bit resolution) due to increased circuit area, complexity, and calibration requirements, often resulting in high die costs and long calibration paths.
Innovation Solution
A segmented DAC circuit utilizing an interpolation resistor DAC (RDAC) with a resistor-2R (R-2R) DAC and a resistor ladder, along with a buffer amplifier, to generate highly accurate analog output signals with reduced complexity and cost, eliminating the need for an interpolation amplifier and minimizing calibration memory and time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional DAC circuits use increased number of switches and resistor elements to achieve higher bit accuracy, then DAC accuracy is improved, but circuit area and device complexity increase significantly
Solution Approach 1:
The patent divides the DAC circuit into multiple segments: an R-2R DAC segment for MSB conversion and a resistor ladder segment for ISB conversion. This segmentation allows each segment to use optimized component configurations, reducing overall circuit complexity while maintaining high accuracy. The R-2R segment handles the most significant bits with a compact structure, while the resistor ladder handles intermediate bits with fewer components than a full-resolution DAC would require.
Solution Approach 2:
The patent introduces interpolation in the bit-significance dimension by treating intermediate significant bits differently from standard binary weighting. The resistor ladder provides interpolated voltage levels between the MSB steps, effectively adding a dimensional approach to voltage generation that reduces the number of discrete switches and resistors needed while maintaining precision.
2Measurement precision
If conventional DAC circuits increase the number of switches and resistor elements for higher bit accuracy, then DAC accuracy is improved, but circuit area increases
Solution Approach 1:
By segmenting the DAC into R-2R and resistor ladder portions, the patent reduces the total component count. The R-2R segment uses a compact repeating structure for MSB bits, and the resistor ladder uses fewer components than a full binary-weighted ladder would require, thereby reducing overall circuit area while maintaining high accuracy.
Solution Approach 2:
The patent merges the R-2R DAC output with the resistor ladder output through an interpolation amplifier that combines both signals. This merging allows the circuit to achieve high-resolution conversion without implementing a complete high-resolution DAC structure, thus reducing the total number of switches and resistors needed and shrinking circuit area.
3Measurement precision
If conventional DAC circuits provide high bit accuracy, then DAC accuracy is improved, but calibration memory and calibration time increase
Solution Approach 1:
The segmented architecture allows calibration to be performed separately on the R-2R segment and the resistor ladder segment. Each segment can be calibrated independently with fewer calibration points required compared to calibrating a complete high-resolution DAC, thereby reducing calibration time and memory requirements while maintaining overall high accuracy.
Solution Approach 2:
The R-2R DAC provides a preliminary analog output that establishes the major voltage steps. The resistor ladder then performs preliminary interpolation to establish intermediate levels. This preliminary action by each segment reduces the calibration burden on the final interpolation amplifier, as the input signals are already well-defined, reducing calibration time and memory needs.
Data Source
AI summary
A integrated circuit device includes digital-to-analog converter (DAC) circuitry including a resistor DAC that includes a resistor-two-resistor DAC configured to receive a first sub-word that includes a most significant bit (MSB) of a digital input signal and to output an analog output signal representative of the first sub-word, a resistor ladder configured to receive the analog output signal and a second sub-word that includes an intermediate significant bit (ISB) of the digital input signal and to generate an analog interpolated signal. The resistor ladder includes a plurality of resistor elements connected in series with one another to define a plurality of tap nodes, wherein a respective tap node is arranged between every two adjacent ones of the resistor elements, and a switching circuit having plurality of switches, wherein each switch is configured to selectively connect a respective one of the tap nodes to an output of the resistor ladder to generate the analog interpolated signal.