Interpolation Resistor DAC Segmentation for 16-Bit Precision
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Solution Overview
Problem
Conventional digital-to-analog converter (DAC) circuits for microcontrollers face challenges in achieving high accuracy (e.g., 16-bit resolution) due to increased circuit area, complexity, and calibration requirements, often resulting in high die costs and long calibration paths.
Innovation Solution
A segmented DAC circuit utilizing an interpolation resistor DAC (RDAC) with a resistor-two-resistor (R-2R) DAC and a resistor ladder, combined with a buffer amplifier, to generate highly accurate analog output signals with reduced complexity and cost, eliminating the need for an interpolation amplifier.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional DAC circuits use increased bit accuracy to achieve high resolution, then measurement precision is improved, but device complexity increases significantly
Solution Approach 1:
The patent divides the DAC circuit into multiple independent segments: an R-2R ladder network for MSB conversion and a resistor string for LSB interpolation. Each segment handles specific bit ranges, allowing independent optimization and reducing overall circuit complexity while maintaining high resolution accuracy.
Solution Approach 2:
The patent transitions from a single-dimensional approach (one large resistor string) to a two-dimensional segmented architecture combining R-2R ladder and resistor string. This dimensional change enables parallel processing of different bit segments, reducing complexity while preserving measurement precision.
2Measurement precision
If conventional DAC circuits increase the number of switches and resistor elements for higher accuracy, then measurement precision is improved, but area occupied increases
Solution Approach 1:
By segmenting the DAC into R-2R ladder and resistor string portions, each handling specific bit ranges, the patent reduces the total number of switches and resistors needed compared to a single high-resolution resistor string, thereby reducing circuit area while maintaining accuracy.
Solution Approach 2:
The patent uses the R-2R ladder structure as a compact alternative to traditional resistor string implementations for MSB conversion. The R-2R topology requires fewer physical components while achieving the same functional result, reducing circuit area occupation.
3Measurement precision
If conventional DAC circuits implement high bit accuracy, then measurement precision is improved, but calibration time increases
Solution Approach 1:
The segmented architecture allows calibration to be performed independently on each segment (R-2R ladder and resistor string). This modular calibration approach reduces total calibration time compared to calibrating a single high-resolution DAC, as each segment can be calibrated separately and in parallel.
Solution Approach 2:
The patent incorporates preliminary calibration mechanisms where offset and gain corrections are applied separately to each segment before final combination. This preliminary calibration of individual segments simplifies the overall calibration process and reduces total calibration time while maintaining high measurement precision.
4Measurement precision
If conventional DAC circuits use more calibration memory for high accuracy, then measurement precision is improved, but device complexity increases
Solution Approach 1:
By dividing calibration data storage into separate memory segments for the R-2R ladder and resistor string portions, the patent reduces the total calibration memory required compared to storing calibration data for a single high-resolution DAC. Each segment requires calibration memory proportional to its resolution rather than the total resolution.
Data Source
AI summary
A segmented digital-to-analog converter (DAC) circuit includes an interpolation resistor DAC (RDAC) and a buffer amplifier. The interpolation RDAC includes a resistor-two-resistor (R-2R) DAC and a resistor ladder. The R-2R DAC is configured to receive a first subword and generate an analog output signal with a voltage representative of the first subword. The first subword has an integer number M bits that include a most significant bit (MSB) of a digital input signal. The resistor ladder is configured to receive the analog output signal and a second subword and generate an analog interpolated signal. The second subword has an integer number I bits that include an intermediate significant bit (ISB) of the digital input signal The buffer amplifier is configured to receive the analog interpolated signal and generate an output signal for the segmented DAC.