R4MDC FFT Processor Integrated Memory Bank

Solution Overview

Problem

Existing R4MDC-based pipelined FFT processors face challenges with data input delay and high memory usage due to the requirement for a double buffer and delay elements.

Innovation Solution

The integration of a double buffer and a delay element into a single memory bank within the FFT processor, allowing for efficient data processing and reduced latency by eliminating separate delay elements and optimizing memory usage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a double buffer and delay elements are used in the input unit of an R4MDC-based FFT processor, then data can be simultaneously received and processed, but data input is delayed and a large amount of memory is required

Engineering Contradiction:

Improveprocessing speedVSAvoiddata input delay

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The patent merges the double buffer and delay elements into a single integrated memory structure. The first memory bank serves both as a double buffer for simultaneous data reception and processing, and as a delay element for providing delayed data to the butterfly units. This integration eliminates the need for separate delay elements and reduces the overall memory requirement by half compared to traditional R4MDC structures that use both double buffer and delay elements separately.

Inventive Principle:

Principle #5Merging (Combining)

2Productivity

If a double buffer and delay elements are used in the input unit of an R4MDC-based FFT processor, then data can be simultaneously received and processed, but a large amount of memory is required

Engineering Contradiction:

Improveprocessing speedVSAvoidmemory usage

Core Design Contradiction:

ProductivityVSQuantity of substance

Solution Approach 1:

The patent merges the double buffer and delay elements into a single integrated memory structure. The first memory bank serves both as a double buffer for simultaneous data reception and processing, and as a delay element for providing delayed data to the butterfly units. This integration eliminates the need for separate delay elements and reduces the overall memory requirement by half compared to traditional R4MDC structures that use both double buffer and delay elements separately.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The first memory bank is designed to perform multiple functions: it acts as a double buffer for simultaneous data input and processing, and simultaneously serves as a delay element for providing delayed data to the butterfly units. This multi-functionality eliminates the need for separate dedicated delay memory, thereby reducing the total memory requirement while maintaining the high processing speed of the R4MDC structure.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Ease of operation

If separate delay elements are used in addition to a double buffer, then data delay is achieved, but device complexity increases

Engineering Contradiction:

Improvedata delay capabilityVSAvoidstructure complexity

Core Design Contradiction:

Ease of operationVSDevice complexity

Solution Approach 1:

The patent merges the double buffer and delay elements into a single integrated memory structure. The first memory bank serves both as a double buffer for simultaneous data reception and processing, and as a delay element for providing delayed data to the butterfly units. This integration eliminates the need for separate delay elements and reduces the overall memory requirement by half compared to traditional R4MDC structures that use both double buffer and delay elements separately.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS20250077614A1FFT processor of r4MDC structure with integrated double buffer and operating method thereof

Publication Date: 2025.03.06 UNIV OF SEOUL IND COOP FOUND

AI summary

The FFT processor having an N-point Radix-4 multi-path delay commutator (R4MDC) structure having a power of 4 comprises: a first memory bank; and second to fourth memory banks configured to delay an output of data.