Memory Module RAA Control Circuitry for Row Hammer Mitigation
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Solution Overview
Problem
Current techniques for detecting and mitigating row hammer or row disturb attacks in DRAM devices, such as perfect row hammer tracking (PRHT) or per row activate counting (PRAC, require significant circuitry overhead and increase row cycle times, leading to performance impacts and complexity issues, making them costly and inefficient, especially in data center deployments.
Innovation Solution
Implementing a rolling accumulated activate (RAA) control circuitry that intercepts commands to DRAM devices, increments activate counts, and alerts the memory controller when a threshold is reached, allowing for directed refresh management (DRFM) commands to mitigate row hammer or row disturb conditions without the need for extensive internal DRAM device circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If perfect row hammer tracking (PRHT) or per row activate counting (PRAC) is implemented in DRAM devices, then row hammer or row disturb attacks can be detected and mitigated, but circuitry overhead increases significantly and row cycle times increase
Solution Approach 1:
The patent extracts the row activation counting function from the DRAM device internal circuitry and relocates it to external circuitry on the memory module. This removes the need for complex internal counters and read-modify-write operations within the DRAM device, significantly reducing circuitry overhead while maintaining row hammer detection capability.
Solution Approach 2:
The patent introduces an intermediary component (external circuitry on the memory module) that mediates between the memory controller and the DRAM device. This intermediary handles the activation counting and threshold monitoring functions, allowing the DRAM device to remain simple while still enabling row hammer detection through coordinated operation with the intermediary circuitry.
2Reliability
If perfect row hammer tracking (PRHT) or per row activate counting (PRAC) is implemented in DRAM devices, then row hammer or row disturb attacks can be detected and mitigated, but row cycle times increase leading to performance impacts
Solution Approach 1:
By extracting the counting logic from internal DRAM circuitry to external memory module circuitry, the patent eliminates the need for read-modify-write operations that previously extended row cycle times. The external circuitry can increment counters without accessing the DRAM memory cells, thus maintaining fast access performance while detecting row hammer attacks.
Solution Approach 2:
The patent implements preliminary action by having external circuitry track activation counts before row hammer conditions can affect the DRAM device. This allows the system to detect and respond to potential row hammer attacks without having to perform time-consuming read-modify-write operations on the DRAM device itself, thereby maintaining performance.
3Reliability
If internal circuitry is added to track row activations in each DRAM device, then row hammer conditions can be monitored, but cost and complexity increase making it prohibitively expensive for data center deployments
Solution Approach 1:
The patent extracts the monitoring function from expensive internal DRAM device circuitry to more cost-effective external circuitry on the memory module. This approach maintains row activation monitoring capability while using less expensive manufacturing processes and components, making the solution economically viable for large-scale data center deployments.
Solution Approach 2:
The patent employs a more economical approach by implementing monitoring circuitry at the memory module level rather than in each expensive DRAM device. This allows for cost-effective deployment across multiple memory modules in data centers, where the lower-cost external circuitry can be replaced or upgraded more easily than modifying individual DRAM devices.
Data Source
AI summary
Examples include techniques for a memory module per row activate counter. The techniques include detecting a row hammer or row disturb condition for a row address at a volatile memory device if an activate count to the row address matches a threshold count. The activate count is maintained by a controller for the memory module. Detection of the row hammer or row disturb condition can cause refresh management actions to mitigate the row hammer or row disturb condition.