Racetrack Memory Array With Integrated MTJ and Sandwiched Electrodes
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional racetrack memory (RTM) manufacturing faces challenges such as high risk of damaging the exposed RT layer during electrode etching, poor yield due to incomplete etching, difficulty in increasing chip density, and impediment to spin torque switching due to the thick MgO barrier, which limits current passage and nucleation of domain walls.
Innovation Solution
The RTM layer sequence is rearranged with a metallization layer forming one pair of electrodes as the bottom layer and another as the outermost layer, sandwiching the RT and MTJ layers, allowing for minimized footprint, increased on-off TMR ratio, and reduced voltage and current density, enabling efficient nucleation and thermal stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the RT layer is arranged on the bottom and MTJ layer on top with electrodes on top for read/write operations, then the device structure is conventional and manufacturing is straightforward, but the exposed RT layer is at high risk of damage during etching of the top metallic layer and the yield is poor
Solution Approach 1:
The patent inverts the conventional layer arrangement by placing the MTJ layer on the bottom and the RT layer on top. This inversion allows the RT layer to be protected by subsequent layers during manufacturing, eliminating the risk of over-etching damage while maintaining conventional manufacturing processes. The inverted structure enables the read/write electrodes to be formed without exposing the delicate RT layer to harmful etching processes.
Solution Approach 2:
The patent transitions from a planar electrode arrangement to a three-dimensional stacked configuration where electrodes are distributed across multiple layers (bottom and top). This dimensional change allows simultaneous access to the RT layer from both sides, enabling read/write operations while protecting the RT layer from damage during electrode formation.
2Ease of manufacture
If electrodes are arranged all on top for interconnection, then the manufacturing is simple, but the chip density cannot be increased due to large footprint and distance between electrodes
Solution Approach 1:
The patent utilizes vertical stacking to arrange electrodes in multiple layers (bottom and top) rather than spreading them out in a single plane. This three-dimensional arrangement dramatically reduces the horizontal footprint of the device while maintaining all necessary electrical connections, thereby increasing chip density without complicating the manufacturing process.
3Strength
If a thick MgO barrier is used between MTJ layer and RT layer, then the barrier strength is sufficient, but spin torque switching is impeded or impossible due to limited voltage across the barrier
Solution Approach 1:
The patent extracts or removes the thick MgO barrier layer that was preventing spin torque switching. By eliminating this barrier, high currents can now pass through to enable domain wall nucleation and spin torque switching operations. The barrier function is replaced by the inherent magnetic properties of the layered structure, allowing both protection and electrical functionality.
4Ease of manufacture
If the RT layer is exposed for electrode manufacturing, then the manufacturing process is straightforward, but the RT layer is damaged during etching of the metallic layer
Solution Approach 1:
The patent inverts the manufacturing sequence by forming electrodes on the bottom layer first, then stacking subsequent layers including the RT layer. This inversion ensures the RT layer is never exposed during electrode manufacturing, completely eliminating the risk of over-etching damage while maintaining manufacturing simplicity.
Solution Approach 2:
The patent performs the electrode formation action preliminarily, before the RT layer is deposited. By creating the electrode structure first and then stacking protective layers over it, the RT layer is shielded from all subsequent etching processes, preventing damage while maintaining manufacturing efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes device footprint, enhances on-off TMR ratio, improves thermal stability, and increases writing speed by reducing stray tunneling current and channel resistance, while allowing for efficient domain wall nucleation and scaling down of the device.
Implementation Method 1
the MTJ is used to read out the device by sensing the magnetization of the strip as domain walls are shifted along the racetrack
Implementation Method 2
the most advantageous racetracks are formed from thin magnetic layers that exhibit a significant perpendicular magnetic anisotropy (PMA) which means that the magnetization either points out of or into the substrate-plane
Implementation Method 3
Multiple magnetic domain walls are shifted through and along the racetrack driven by current pulses which are passed along the racetrack
Implementation Method 4
Recent developments, especially spin-orbit torques (SOTs) and exchange coupling torques (ECTs) yield an highly efficient current-induced DW motion
Implementation Method 5
enabling efficient nucleation and thermal stability
Implementation Method 6
Recent developments, especially spin-orbit torques (SOTs) and exchange coupling torques (ECTs) yield an highly efficient current-induced DW motion
Data Source
AI summary
The present invention relates to racetrack memory array devices, and more specifically, to a manufacturing method of racetrack memory arrays with integrated magnetic tunnel junction for read/write.