Radiation-Hardened Bias Circuit Layout for Low-Noise Power Management
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Solution Overview
Problem
Existing power management devices are not adequately designed to withstand radiation environments, leading to noise interference and inefficiencies in providing multiple voltage biases for electronic components, which is critical for space and radiation-hardened applications.
Innovation Solution
A radiation-hardened low noise power management device incorporating a circuit module with specific transistor arrangements, well ties, substrate ties, and configuration circuitry, including triple mode redundant flip-flops, to provide stable voltage biases and mitigate radiation effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional power management devices are used in radiation environments, then device complexity is reduced, but reliability deteriorates due to radiation susceptibility
Solution Approach 1:
The power management device is divided into separate doped regions (N-well and P-well) with dedicated well ties and substrate ties for each region. This segmentation isolates radiation effects to specific regions, preventing propagation across the entire device while maintaining overall reliability.
Solution Approach 2:
Well ties and substrate ties are pre-positioned at predetermined distances from transistors to create protective zones before radiation-induced charge carriers can affect the transistor operation. This preemptive structuring cushions the transistors against radiation effects.
2Object-generated harmful factors
If well ties and substrate ties are added to the circuit module, then noise is reduced, but device complexity increases
Solution Approach 1:
Well ties are placed locally within the doped region near sensitive transistors, and substrate ties are positioned at the interface between doped and undoped regions. This localized placement provides noise reduction exactly where needed without adding complexity throughout the entire device.
Solution Approach 2:
Well ties act as intermediary elements between the doped region and the substrate, providing a controlled path for charge carriers. This intermediary structure mediates the interaction between radiation-induced charges and the transistor, reducing noise while adding minimal complexity.
3Reliability
If transistors are disposed in doped regions with well ties, then radiation hardness is improved, but manufacturing precision requirements increase
Solution Approach 1:
The doped regions, well ties, and substrate ties are pre-configured in the device structure before transistor placement. This preliminary structuring provides clear guidelines and reference points for transistor placement, reducing the precision burden during the placement process while maintaining radiation hardness.
Data Source
AI summary
A power management device is provided including a circuit module configured to provide a set of voltage biases for one or more target devices. The circuit module includes a set of first transistors of a first type and disposed in a doped region, a set of well ties disposed in the doped region and located a predetermined distance from the set of first transistors, a set of second transistors of a second type and disposed outside the doped region, and a set of substrate ties disposed between the doped region and the set of second transistors.