Rad-Hard CMOS IC Design via EDA Parameter Tuning
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Solution Overview
Problem
Current radiation-hardened integrated circuits (ICs) are costly and have a longer time-to-market due to the need for special materials and processes, limiting their availability for critical applications, and there is a lack of effective electronic design automation (EDA) tools to enhance radiation hardness in commercial CMOS processes.
Innovation Solution
A computer-implemented method and system using EDA tools that provide rad-hard design layout methods, rules, and verification techniques, along with rad-hard device models and libraries, to enhance the radiation hardness of ICs designed in standard CMOS processes, allowing for the conversion of existing commercial ICs into radiation-hardened versions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If special materials and dedicated fabrication processes are used for radiation-hardened ICs, then radiation hardness is improved, but cost and time-to-market increase
Solution Approach 1:
The patent changes the design parameters of standard CMOS transistors (channel width, length, doping profiles, oxide thickness) to achieve radiation hardness without requiring special materials or processes. By modifying transistor geometry and electrical parameters within commercial process capabilities, the invention achieves >100 krad hardness using standard 0.18-micron CMOS, thereby reducing time-to-market while maintaining radiation protection
Solution Approach 2:
The patent makes standard commercial CMOS processes multi-functional by demonstrating they can produce both commercial-grade and radiation-hardened ICs using the same fabrication line. The universal CMOS process is adapted through design techniques (well-tied configurations, guard rings, specific transistor sizing) to achieve radiation hardness, eliminating the need for separate rad-hard process facilities and accelerating deployment
2Reliability
If special materials and dedicated fabrication processes are used for radiation-hardened ICs, then radiation hardness is improved, but manufacturing cost increases
Solution Approach 1:
The patent achieves radiation hardness by changing transistor design parameters (W/L ratios, doping concentrations, oxide thicknesses) that can be implemented within standard CMOS process capabilities. This avoids the need for expensive special materials like silicon-on-insulator substrates and dedicated rad-hard fabrication facilities, thereby reducing manufacturing cost while achieving >100 krad hardness
Solution Approach 2:
The patent copies and adapts proven radiation-hardening techniques from specialized processes into standard CMOS design rules. By creating a rad-hard PDK that replicates the effectiveness of special processes through standardized design cells and layout rules, the invention achieves radiation protection at commercial process costs
3Reliability
If manual full custom design flow is used for rad-hard ICs, then radiation hardness is improved, but design complexity and skill requirements increase
Solution Approach 1:
The patent performs preliminary radiation-hardening actions by pre-designing standard cells and creating a complete PDK with built-in rad-hard features (guard rings, well ties, optimized transistor geometries). This preliminary preparation allows subsequent designs to automatically inherit radiation hardness through standard design flows, reducing design complexity and eliminating the need for manual rad-hard optimization by individual designers
Solution Approach 2:
The patent enables designs to self-service their own radiation hardening through automated EDA tool integration. The rad-hard PDK includes design rules and verification methodologies that automatically ensure radiation hardness compliance during standard design flows, removing dependence on designer expertise and manual intervention while maintaining high radiation protection standards
4Productivity
If standard commercial CMOS processes are used without rad-hard design techniques, then cost and time-to-market are reduced, but radiation hardness deteriorates
Solution Approach 1:
The patent applies parameter changes to standard CMOS transistor designs (increased oxide thickness, adjusted doping profiles, modified W/L ratios) that push the boundaries of commercial process capabilities to achieve enhanced radiation hardness. These parameter modifications allow standard processes to produce devices with >100 krad hardness, simultaneously maintaining fast time-to-market while reducing radiation susceptibility
Solution Approach 2:
The patent applies local quality enhancements at critical locations within the circuit (input protection circuits, reference voltage generators, bias circuits) using specific rad-hard design techniques. By concentrating radiation hardening efforts where they are most needed rather than uniformly across all circuits, the invention achieves effective radiation protection while maintaining standard process efficiency and fast development cycles
Data Source
AI summary
A method, system, and computer program product include electronic design automation (EDA) tools used with standard CMOS processes to design and produce radiation-hardened (rad-hard) integrated circuits (ICs) having a predictable level of radiation hardness while maintaining a desired level of performance and tracking circuit area. The tools include rad-hard design rule checking (DRC) decks, rad-hard SPICE models, and rad-hard cell libraries. A rad-hard parasitic components extraction process makes use of rad-hard DRC rules to locate occurrences of parasitic devices, calculate their effects on circuit performance, and return this information to layout and circuit simulation tools. Changes to the layout are suggested and implemented with varying degrees of automation. Some of these tools can be provided as components of a rad-hard process design kit (PDK). They can be used in conjunction with commercial EDA tools to facilitate the incorporation of rad-hard features into new or existing IC designs.