Radiation-Hardened 32-Bit I/O Expander for Serial-to-Parallel Control
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Solution Overview
Problem
Existing I/O expanders are not radiation hardened and are limited to 8 or 16 general purpose I/O pins, making them unsuitable for harsh environments like space applications, and lack the flexibility to expand serial interfaces to higher bit configurations.
Innovation Solution
A radiation hardened 32-bit remote I/O expander ASIC that converts serial interfaces (I2C or SPI) to a parallel bus, featuring 0.25 μm CMOS process, triple voted flip flops, and 32-bit digital I/O ports with programmable functionality, suitable for miniaturized instrument electronics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If prior art I/O expanders (MCP23017, PCA9502) are used, then I/O expansion capability is provided, but radiation hardness is insufficient for harsh environments like space applications
Solution Approach 1:
The patent applies radiation hardening techniques to modify the physical and structural parameters of the CMOS circuit, making it resistant to radiation effects. This includes using radiation-tolerant design methodologies and processes that change the device's physical characteristics to withstand harsh radiation environments while maintaining operational functionality
Solution Approach 2:
The patent creates a radiation-hardened version of the I/O expander by replicating the functional architecture of commercial devices (MCP23017, PCA9502) but implementing it with radiation-hardened standard cells. This copying approach preserves the proven functionality while replacing vulnerable components with radiation-tolerant equivalents
2Adaptability or versatility
If prior art I/O expanders are used, then I/O expansion is provided, but bit expansion capability is limited to 8 or 16 pins
Solution Approach 1:
The patent segments the 32-bit parallel bus into multiple 8-bit ports (PORTA, PORTB, PORTC, PORTD), each independently controllable through serial interface commands. This segmentation allows flexible configuration of I/O pins without requiring a completely different device architecture, enabling bit expansion beyond the 8 or 16-pin limitations of prior art
Solution Approach 2:
The patent transitions from the serial dimension (1-wire or 2-wire interfaces) to the parallel dimension (32-bit bus), effectively adding dimensional capacity. This allows the system to expand I/O capability from limited serial communication to high-capacity parallel operations while maintaining a compact serial control interface
3Adaptability or versatility
If a larger microcontroller is used to provide additional I/O signals, then I/O expansion is achieved, but reengineering cost and complexity increase substantially
Solution Approach 1:
The patent introduces an I/O expander device as an intermediary between the microcontroller and external devices. This intermediary handles the I/O expansion functionality, allowing the original microcontroller to remain unchanged. The expander translates serial commands from the microcontroller into parallel I/O operations, eliminating the need for costly reengineering of the microcontroller itself
4Device complexity
If serial interface is used instead of parallel interface, then fewer signal pins are required, but I/O expansion capability is reduced
Solution Approach 1:
The patent implements a nested architecture where a compact serial interface (1-wire or 2-wire) is embedded within a larger 32-bit parallel I/O system. The serial interface acts as a control layer that manages and expands the parallel I/O capabilities, allowing high expansion capability to be achieved through a low-pin-count serial connection by nesting control functions within the serial protocol
Data Source
AI summary
The invention is a microcircuit configured as a compact, radiation hardened, low-power general purpose I/O expander. The expander may be controlled by an external microcontroller or central processing unit through a serial interface. The expander provides a simple solution to miniaturize static parallel I/O signals using a simplified serial interface such as I2C or SPI.