Recessed Access Device Transistor Trench Etching Control
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Solution Overview
Problem
The miniaturization of semiconductor devices leads to the short channel effect, where transistors activate without the application of threshold voltage due to excessively small channel widths, and the etching process for recessed access device (RAD) transistors is cumbersome, resulting in low productivity, high costs, and increased contamination risks due to unreliable etch depth estimation.
Innovation Solution
A semiconductor device and manufacturing method involving a substrate with a buried layer, gate electrodes penetrating through it, and impurity regions on either side, along with a dummy electrode and capping layer, where the buried layer is exposed through the dummy electrode, and a dielectric liner is used to control the etching process, allowing for precise adjustment of trench depths and dopant concentrations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the channel width is reduced to miniaturize the transistor, then the device size decreases, but the short channel effect occurs causing the transistor to activate without threshold voltage
Solution Approach 1:
The patent transitions from a planar channel structure to a three-dimensional trench structure. The gate electrode is positioned within a trench formed in the semiconductor substrate, creating a channel that wraps around the gate electrode in multiple dimensions. This vertical and lateral extension of the channel within the trench provides a wider effective channel area without increasing the lateral footprint of the transistor, thereby maintaining miniaturization while improving channel control and reducing short channel effects.
Solution Approach 2:
The gate electrode is nested within the trench structure, which itself is nested within the semiconductor substrate. The channel region is formed around the gate electrode inside the trench, creating a nested configuration where the gate is surrounded by the channel which is surrounded by the trench walls. This nested structure allows for better electrostatic control of the channel while maintaining a compact form factor.
2Manufacturing precision
If the etching process is continuously monitored by interrupting it for depth measurement, then the etch depth precision improves, but the productivity decreases and contamination risk increases
Solution Approach 1:
The etching process is designed to be self-limiting by using the exposed buried layer as a natural endpoint indicator. When the trench etching reaches the buried layer, the etching process automatically stops or significantly slows down due to the different etch rates between the substrate and the buried layer. This eliminates the need for continuous interruption and measurement, allowing the etching to proceed continuously until the buried layer is exposed, thereby maintaining precision while improving productivity and reducing contamination risk.
Solution Approach 2:
The patent uses the visual or detectable change that occurs when the buried layer is exposed during etching as an endpoint indicator. The exposed buried layer presents a distinct appearance or signal compared to the unetched substrate, allowing operators or automated systems to detect when the target etch depth has been reached without needing to interrupt the process for measurements. This continuous monitoring approach maintains precision while avoiding the productivity losses associated with repeated interruptions.
3Manufacturing precision
If the trench etching is performed to precisely control the gate depth, then the overlay between gate and source/drain junctions improves, but the process complexity and cost increase
Solution Approach 1:
The buried layer serves as a self-referencing endpoint for the etching process. The etching continues until the buried layer is naturally exposed, which automatically provides the correct depth without requiring complex real-time measurements or adjustments. This self-limiting mechanism simplifies the process control while maintaining precise depth control, reducing both process complexity and cost.
Solution Approach 2:
The buried layer is pre-formed in the substrate before the trench etching process begins. This preliminary action creates a predetermined depth reference that guides the subsequent etching process. By preparing the buried layer in advance, the patent establishes a built-in depth marker that simplifies the etching control, eliminating the need for complex in-process measurements and adjustments.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables precise control over the etching process, improving the quality and productivity of semiconductor devices by forming a wider channel without increasing lateral space, reducing contamination risks, and enhancing the accuracy of etch depth estimation.
Implementation Method 1
the etching process must be closely monitored by periodically interrupting it to measure the etched depth in the semiconductor wafer
Implementation Method 2
introducing dopants into the substrate to form impurity regions on the buried layer
Data Source
AI summary
The present disclosure provides a semiconductor device including a recessed access device (RAD) transistor and a method of manufacturing the semiconductor device. The semiconductor device includes a substrate, a gate electrode, and a plurality of impurity regions. The substrate includes a buried layer. The gate electrode is disposed in the substrate and penetrates through the buried layer. The plurality of impurity regions are disposed in the substrate and on either side of the gate electrode.