Recessed Access Device Word Line Etch Control
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Solution Overview
Problem
The challenge in manufacturing recessed access device (RAD) transistors is the unreliable estimation of etching time due to variations in the etching process, leading to low productivity, high costs, and increased opportunities for contamination or faults in the photoresist pattern, especially with increasing DRAM bit density.
Innovation Solution
A method involving creating trenches in a substrate, forming dielectric and conductive layers, and accurately controlling the etch depth of the first conductive layer to form word lines, which includes steps like forming a sacrificial layer, etching to create trenches, depositing dielectric and diffusion barrier layers, and recessing the conductive layers to ensure precise etching and improved semiconductor device quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If timed etching with periodic interruption and measurement is used to control etch depth, then etching precision can be improved, but productivity decreases and costs increase
Solution Approach 1:
The patent applies preliminary action by forming a sacrificial layer and depositing dielectric and conductive layers with predetermined thicknesses before the etching step. The etch depth is pre-determined by the thickness of these deposited layers, eliminating the need for periodic interruptions and measurements during etching. This approach maintains precise etch depth control while continuously improving productivity.
2Manufacturing precision
If timed etching process is used, then etching precision can be maintained, but the opportunity for contamination and faults in photoresist pattern increases
Solution Approach 1:
The patent extracts the need for periodic interruptions and measurements from the etching process by using a sacrificial layer structure that pre-determines etch depth. The etching proceeds continuously without stopping, removing the opportunities for contamination and photoresist pattern faults that would otherwise occur during repeated interruptions.
3Ease of manufacture
If etching rate consistency is assumed for timing estimation, then process simplicity is maintained, but etching depth control reliability deteriorates
Solution Approach 1:
The patent introduces a sacrificial layer as an intermediary that mediates between the simple timing-based etching process and the requirement for precise depth control. The sacrificial layer's predetermined thickness acts as a physical reference that ensures accurate etch depth regardless of etching rate variations, maintaining both process simplicity and control reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method allows for accurate control of etch depth, enhancing the quality of semiconductor devices by reducing the reliance on timed etching and minimizing contamination risks, thereby improving productivity and reducing costs.
Implementation Method 1
the etching process must be closely monitored by periodically interrupting it to measure the etched depth
Implementation Method 2
depositing a first conductive layer on the dielectric film to partially fill the trench
Data Source
AI summary
The present disclosure provides a method of manufacturing a semiconductor device. The method includes steps of creating at least one trench in a substrate; forming a dielectric film on the substrate in the trench; depositing a first conductive layer on the dielectric film to partially fill the trench; depositing an insulative film on the first conductive layer; depositing a second conductive layer to bury the insulative film; and recessing the first conductive layer, until the insulative film is entirely removed. Due to the deposition of the insulative film on the first conductive layer, the etch depth of the superfluous first conductive layer can be accurately controlled.