Radar Peak Detection Circuit With Bit-Oriented Bitmap Processing
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Solution Overview
Problem
Existing radar signal processing systems face inefficiencies in bitwise operations, leading to high latency and energy consumption, particularly in scenarios requiring rapid processing like autonomous vehicles, due to the complexity of processing bitmaps representing radar data.
Innovation Solution
An integrated radar signal processing circuit with a bit-oriented hardware accelerator that processes individual bits of detection bitmaps, reducing the need for extensive bitwise operations typically performed by CPUs or DSPs, thereby accelerating the processing of radar data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional radar signal processing methods are used, then processing can be performed, but latency and energy consumption are high
Solution Approach 1:
The processing task is segmented into two independent bitmap operations: a first detection bitmap identifying peaks along the first index and a second detection bitmap identifying peaks along the second index. This segmentation allows parallel processing and reduces the complexity of each operation, thereby reducing latency and energy consumption while maintaining processing speed.
2Loss of energy
If conventional radar signal processing methods are used, then processing can be performed, but energy consumption is high
Solution Approach 1:
The processing task is segmented into two independent bitmap operations: a first detection bitmap identifying peaks along the first index and a second detection bitmap identifying peaks along the second index. This segmentation allows parallel processing and reduces the complexity of each operation, thereby reducing latency and energy consumption while maintaining processing speed.
3Ease of operation
If bitwise operations are performed using conventional methods, then processing can be completed, but the load on CPUs or DSPs is high
Solution Approach 1:
The complex bitwise operations are extracted from the general-purpose CPU or DSP and implemented as dedicated hardware circuits. The first detection circuit and second detection circuit independently process the first and second bitmaps respectively, removing the computational burden from the CPU/DSP and improving processing efficiency while reducing overall system complexity.
Data Source
AI summary
A circuit includes a signal processing unit to generate a radar map represented by an array with a first index and a second index, and a peak detection unit to identify potential targets in the radar map. Within the peak detection unit, a first peak detection sub-unit scans the radar map along the first index and stores a first detection bitmap that identifies peaks as a function of the first index, and a second peak detection sub-unit scans the radar map along the second index and outputs a second detection bitmap that identifies peaks as a function of the second index. The first detection bitmap and the second detection bitmap identify the peaks using a single bit. A hardware accelerator processes individual bits of the first detection bitmap and of the second detection bitmap.