Hardware Accelerator Engine for Automotive Radar CFAR Processing
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Solution Overview
Problem
Software-based Constant False Alarm Rate (CFAR) processing in radar systems for automotive safety applications is time-consuming and inefficient, leading to impaired performance and increased costs due to high computing loads and long scanning times, which complicates the reliable detection of valid targets amidst noise and interference.
Innovation Solution
A hardware accelerator engine is designed to map complex CFAR processing procedures, incorporating features like pseudo-cache memory, concurrent sorting units, and Direct Memory Access (DMA) for reduced processing time and improved performance, enabling bi-dimensional CFAR processing and effective cloud clutter suppression.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If software-based CFAR processing is used on powerful processors, then CFAR procedures can be implemented, but data processing time increases significantly due to high computing loads and memory accesses
Solution Approach 1:
The patent replaces software-based CFAR processing with a dedicated hardware accelerator engine. This hardware engine implements CFAR processing through specialized circuitry including sorting networks, comparators, and memory structures, substituting the general-purpose software execution with purpose-built hardware logic that operates in parallel and eliminates the need for complex memory accesses and computational overhead inherent in software implementations.
2Reliability
If software-based CFAR processing is used, then CFAR procedures can be implemented, but system cost increases due to requirements for powerful processors
Solution Approach 1:
The patent replaces expensive powerful general-purpose processors with a cost-effective hardware accelerator engine. This specialized hardware implementation achieves the required CFAR processing capability through dedicated circuitry, eliminating the need for high-performance CPUs or GPUs and significantly reducing system cost while maintaining or improving processing performance.
3Reliability
If sophisticated CFAR procedures are implemented, then target detection reliability improves, but processing time increases making real-time detection difficult
Solution Approach 1:
The patent segments the CFAR processing function into distinct hardware modules within the accelerator engine, including separate sorting networks for different dimensions, multiple comparators for different threshold calculations, and dedicated memory structures for reference and guard cells. This segmentation allows parallel processing of multiple CFAR operations simultaneously, achieving sophisticated detection algorithms at high speeds suitable for real-time automotive radar applications.
Solution Approach 2:
The hardware accelerator engine implements dynamic and reconfigurable processing capabilities, allowing the CFAR algorithm parameters such as window sizes, guard cell configurations, and sorting depth to be adjusted in real-time based on radar operating conditions. This dynamic adaptation enables the system to maintain high processing speeds while adjusting detection sensitivity and reliability parameters according to environmental conditions.
Data Source
AI summary
An accelerator device for use in generating a list of potential targets in a radar system, such as an anti-collision radar for a motor vehicle, may process radar data signals arranged in cells stored in a system memory. A cell under test in is identified as a potential target if the cell under test is a local peak over boundary cells and is higher than a certain threshold calculated by sorting range and velocity radar data signals arranged in windows. The cells identified as a potential target are sorted in a sorted list of potential targets. The accelerator device may include a double-buffering local memory for storing cell under test and boundary cell data; and a first and a second sorting unit for performing concurrent sorting of the radar data signals arranged in windows and the cells identified as a potential target in pipeline with accesses to the system memory.