Radar Chirp Timing Control with Segmented Parameter Storage
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Solution Overview
Problem
Current automotive radar systems face challenges in efficiently transmitting and configuring large frames of chirps with varying parameters in real-time, requiring extensive software intervention and significant storage for parameter registers.
Innovation Solution
A radar device with a timing control component that generates chirp control signals based on pre-programmed chirp configuration and profile parameters, reducing the need for external software intervention and minimizing storage requirements by using a set of chirp configuration and profile storage components to manage parameter values for multiple sequential chirps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If one set of parameter registers is used for each chirp in a frame, then each chirp can have unique parameter values, but the silicon area required becomes excessively large
Solution Approach 1:
The patent segments the parameter storage into two distinct parts: chirp configuration parameters (stored in a small number of registers) and chirp profile parameters (stored in compact profile storage). This segmentation allows unique parameter combinations for each chirp without requiring a full set of registers for every chirp, thereby reducing silicon area while maintaining parameter uniqueness.
Solution Approach 2:
The patent implements a nested structure where chirp profiles contain multiple related parameters that can be reused across multiple chirps. By nesting common parameters within reusable profiles and only storing unique configuration parameters separately, the system achieves parameter uniqueness per chirp with minimal storage overhead.
2Adaptability or versatility
If multiple sets of parameter registers are allocated for each chirp, then parameter configuration flexibility is improved, but the device complexity and storage requirements increase
Solution Approach 1:
The patent creates reusable chirp profiles that can be referenced by multiple chirps, making the profile storage structure universal and multi-functional. Instead of having dedicated registers for each chirp, the system uses a small number of configuration registers that reference reusable profiles, reducing device complexity while maintaining configuration flexibility.
Solution Approach 2:
The patent pre-organizes common parameter combinations into reusable chirp profiles before chirp transmission. This preliminary organization allows the system to quickly configure individual chirps by selecting and modifying profiles rather than setting each parameter from scratch, reducing both complexity and configuration time.
3Productivity
If software continuously configures chirp parameters in real-time, then parameter updates can keep pace with chirp transmission, but software processing overhead increases
Solution Approach 1:
The patent pre-configures chirp profiles with common parameter sets before chirp transmission begins. During actual chirp transmission, the system only needs to select and slightly modify these pre-configured profiles rather than configuring all parameters from scratch, dramatically reducing real-time software processing overhead while maintaining high configuration speed.
Data Source
AI summary
A radar device is provided that includes a timing control component operable to generate, for each chirp of a sequence of chirps according to a set of chirp configuration parameters and a chirp profile for the chirp, chirp control signals to cause the radar device to transmit the chirp, the timing control component having chirp configuration parameter inputs, chirp profile parameter inputs, a chirp address output, and chirp control signal outputs, a chirp configuration storage component having chirp configuration parameter outputs coupled to corresponding inputs of the configuration parameter inputs of the timing control component, a chirp profile address output, and a chirp address input coupled to the chirp address output, and a chirp profile storage component having chirp profile parameter outputs coupled to the chirp profile parameter inputs of the timing control component; and a chirp profile address input coupled to the chirp profile address output.