Multi-Module Radar Clock Synchronization for Phase-Coherent Sampling
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Solution Overview
Problem
Radar systems with multiple transceiver modules face limitations in spatial and velocity resolution due to phase skew in clock signals, which is exacerbated by imperfections on the PCB and variations over temperature, supply voltage, and aging effects.
Innovation Solution
A radar system with a leader module and follower modules, where each module includes a PLL clock signal generator with a phase comparator, loop filter, oscillator, divide-by-n clock divider, feedback device, and multiplexer, allowing for phase coherent sampling clocks to be generated by selecting clock phases from a feedback differential multiphase divider.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If delay lines are used to align reference clock phases, then phase alignment is improved, but phase noise performance deteriorates and area increases
Solution Approach 1:
The patent implements a feedback mechanism where the phase of the divided clock signal is continuously monitored and compared against a reference phase. A phase detector generates an error signal that feeds back to a voltage-controlled oscillator (VCO) to automatically adjust and maintain phase alignment, eliminating the need for passive delay lines that degrade phase noise
Solution Approach 2:
The patent replaces the mechanical/electrical delay line structure with an all-digital phase-locked loop system. Instead of using physical delay elements that introduce phase noise, the solution uses digital phase detection, comparison, and correction mechanisms that maintain signal integrity while achieving precise phase alignment
2Measurement precision
If delay lines are used to adjust ADC sampling clock phase, then phase alignment is improved, but power consumption increases and area increases
Solution Approach 1:
The patent employs a feedback-controlled phase adjustment mechanism where the phase of the ADC sampling clock is continuously monitored and corrected. A phase detector compares the actual phase with the desired phase, and the resulting error signal adjusts the clock phase dynamically, replacing power-hungry delay lines with an efficient digital control loop
Solution Approach 2:
The patent implements a dynamic phase adjustment capability where the sampling clock phase can be adaptively changed based on detected phase errors. The system transitions from static delay line configurations to a dynamic feedback-controlled system that adjusts phase in real-time, reducing power consumption while maintaining alignment precision
3Measurement precision
If manual phase adjustment is performed to remove production spread, then phase alignment is improved, but manufacturing cost increases and manufacturing complexity increases
Solution Approach 1:
The patent implements a self-calibrating system that automatically compensates for production variations. During initial operation, the system performs self-testing and automatically adjusts phase parameters to optimal values, eliminating the need for expensive manual calibration processes and reducing manufacturing complexity
Solution Approach 2:
The patent utilizes programmable phase parameters that can be automatically adjusted based on measured performance. The system allows for digital modification of phase control parameters to compensate for manufacturing tolerances, replacing costly manual adjustment procedures with automated parameter optimization
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables phase alignment of ADC sampling clocks across modules with a resolution of less than 100 ps and a duty cycle of 50%, improving the spatial and velocity resolution of the radar system without the need for costly delay lines or complex control circuits.
Implementation Method 1
each of the leader and follower modules comprising a phase locked loop, PLL, clock signal generator
Implementation Method 2
a divide by n clock divider connected to receive the second clock signal from the second oscillator and to output 2n phase shifted clock signals at a third frequency
Data Source
Figure 1
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AI summary
The disclosure relates to a radar system having multiple radar transceiver modules, in which each module has a clock signal that is synchronised with a clock signal generated by a leader transceiver module. Example embodiments include a radar system (400) comprising a plurality of radar transceiver modules (401, 402) mounted to a common PCB (404), the plurality of radar transceiver modules comprising a leader module (401) and one or more follower modules (402), the leader module (401) comprising a first oscillator (403) configured to provide a first clock signal at a first frequency to each follower module (402), each of the leader and follower modules comprising a phase locked loop, PLL, clock signal generator (300), the PLL clock signal generator (300) comprising a divide by n clock divider (304) arranged to output 2n phase shifted clock signals (314) at a third frequency and a multiplexer (306) connected to receive the 2n phase shifted clock signals from the divide by n clock divider (304) and output a third clock signal (308) selected by an input phase select signal (307).