Memory Address Generator for Radar Data Cube Bank Interleaving
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Solution Overview
Problem
Radar data cubes, with increasing dimensions due to advancements in radar front-end design and applications like self-driving cars, no longer fit within internal SRAM memory, necessitating storage in external DRAM while maintaining high image data throughput and conventional radar signal processing performance.
Innovation Solution
A memory address generator that generates physical memory addresses based on a logical start address and burst size, mapping consecutive logical start addresses to different memory rows and banks, thereby avoiding memory row conflicts and optimizing data transfer between SRAM and DRAM, allowing for efficient storage and access of radar data cubes in external DRAM.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If radar data cubes are stored in external DRAM memory, then memory capacity is sufficient for increasing data dimensions, but memory access performance and throughput may deteriorate due to memory row conflicts
Solution Approach 1:
The patent applies segmentation by dividing the DRAM memory into multiple banks (e.g., 8 banks) and implementing a bank interleaving strategy where consecutive logical start addresses are mapped to different memory banks. This segmentation allows parallel access to multiple banks simultaneously, preventing memory row conflicts and maintaining high data throughput while providing sufficient memory capacity for large radar data cubes.
Solution Approach 2:
The patent introduces an additional dimension to the memory address mapping by incorporating bank selection into the address generation process. Instead of linear addressing, the system uses a multi-dimensional address space that includes bank index, row index, and column index, enabling three-dimensional access patterns that optimize both capacity utilization and access performance.
2Quantity of substance
If radar data cubes are stored in external DRAM memory, then memory capacity is sufficient for increasing data dimensions, but memory access complexity increases due to address mapping requirements
Solution Approach 1:
The patent implements preliminary action by pre-configuring the bank interleaving mapping table and pre-calculating the optimal bank selection for each logical address. The memory address generator is designed with built-in logic that automatically determines the appropriate bank based on the logical start address, eliminating the need for complex runtime address translation and reducing access complexity.
Solution Approach 2:
The patent introduces an intermediary component - the memory address generator - that acts as a mediator between the logical address space and the physical DRAM address space. This intermediary translates logical start addresses into physical addresses with automatic bank selection, simplifying the access interface while managing the complexity of multi-bank memory organization.
3Ease of operation
If consecutive logical start addresses are mapped to the same memory bank, then address mapping is simple, but memory row conflicts occur reducing data access efficiency
Solution Approach 1:
The patent applies segmentation by dividing the DRAM memory into multiple banks (e.g., 8 banks) and implementing a bank interleaving strategy where consecutive logical start addresses are mapped to different memory banks. This segmentation allows parallel access to multiple banks simultaneously, preventing memory row conflicts and maintaining high data throughput while providing sufficient memory capacity for large radar data cubes.
Solution Approach 2:
The patent changes the addressing parameter from simple linear addressing to bank-interleaved addressing. The address generation logic dynamically adjusts the bank selection parameter based on the logical start address, creating an alternating access pattern across banks that eliminates row conflicts while maintaining mapping simplicity through systematic parameter variation.
Data Source
AI summary
A device for accessing memory configured to store an image data cube, wherein the memory has memory banks, and each memory bank has memory rows and memory columns. The device includes an input configured to receive a memory access request having a logical start address, which specifies a logical bank, a logical row, and a logical column, and a burst size; and a memory address generator configured to generate physical memory addresses based on the logical start address and the burst size, wherein any consecutive logical start addresses mapped to different memory rows are mapped to different memory banks.