Radar Device Delay Lock Loop Noise Reduction

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Solution Overview

Problem

Radar devices face challenges in accurately detecting object positions due to noise in signal processing, which affects the accuracy of delay calculations and target detection ranges.

Innovation Solution

A radar device configuration incorporating a clock generator, transmitter, receiver, and signal processor that adjusts delays using a delay locked loop (DLL) and voltage-controlled delay line (VCDL) to minimize noise, allowing for precise calculation of target positions based on notification signals and echo signal reception times.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If delay locked loop (DLL) and voltage-controlled delay line (VCDL) are used to adjust delays, then measurement precision of target position is improved, but device complexity increases

Engineering Contradiction:
Improvetarget position detection accuracyVSAvoidsignal processing system complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent implements a delay locked loop (DLL) that uses feedback mechanisms to automatically adjust and optimize delay values. The system measures signal characteristics, compares them against reference values, and dynamically adjusts the VCDL delay settings to minimize noise and maximize detection accuracy, thereby achieving high measurement precision through closed-loop control

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The voltage-controlled delay line (VCDL) serves as an intermediary component between the control system and the signal processing pipeline. It provides precise, continuously adjustable delay control that mediates between the digital control logic and the analog signal processing, enabling fine-tuned noise reduction without requiring complex reconfiguration of the entire system

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If delay is adjusted to minimum value to reduce noise, then signal processing quality is improved, but loss of time in delay adjustment occurs

Engineering Contradiction:
Improvesignal processing qualityVSAvoiddelay adjustment time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system performs preliminary characterization of the delay-range relationship during system initialization or calibration phases. By pre-establishing the optimal delay values for different detection ranges and storing this information in lookup tables, the system can quickly retrieve appropriate delay settings during operation without performing time-consuming real-time optimization, thus reducing noise while minimizing time loss

Inventive Principle:
Principle #10Preliminary action

3Ease of operation

If delay locked loop (DLL) is used for automatic delay adjustment, then ease of operation is improved, but device complexity increases

Engineering Contradiction:
Improvedelay adjustment automationVSAvoidcontrol system complexity
Core Design Contradiction:
Ease of operationVSDevice complexity

Solution Approach 1:

The delay locked loop (DLL) implements self-service functionality by automatically monitoring signal quality metrics and adjusting delay parameters without external intervention. The system continuously evaluates echo signal characteristics and autonomously optimizes delay settings to maintain optimal performance, eliminating the need for manual calibration while managing control complexity through integrated feedback mechanisms

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS11067678B2Radar device using delay
Publication Date: 2021.07.20 ELECTRONICS & TELECOMM RES INST
  • US11067678B2 patent drawing
  • US11067678B2 patent drawing
  • US11067678B2 patent drawing

AI summary

A radar device according to an embodiment of the inventive concept includes a clock generator, a transmitter, a receiver, and a signal processor. The clock generator outputs the transmission clock, outputs the reception clock at the second time after the delay from the first time when the transmission clock is outputted, and generates the notification signal when the delay has the minimum value. The transmitter emits a transmission signal based on the transmission clock. The receiver receives an echo signal corresponding to the transmission signal, and generates a first signal corresponding to the echo signal based on the reception clock. The signal processor obtains a third time point at which a delay has the minimum value based on the notification signal.