Low-Power Radar Detection Receiver Frequency Plan
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Solution Overview
Problem
Current radar detection receivers in WiFi devices consume high power due to the need for continuous monitoring of DFS channels, which is inefficient for battery-fed mobile devices and increases battery life degradation.
Innovation Solution
A low-power radar detection receiver is implemented using a unique frequency plan that employs a finite impulse response (FIR) filter to sample signals at a high rate, while the analog-to-digital converter operates at a lower conversion rate, reducing power consumption by avoiding aliasing effects from nearby WiFi signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a radar detection receiver continuously monitors DFS channels to detect radar signals, then detection reliability is improved, but power consumption increases
Solution Approach 1:
The receiver performs periodic channel availability checks instead of continuous monitoring. The ADC circuit is enabled only during these periodic check periods to detect radar signals, and disabled during normal WiFi operation. This periodic activation maintains radar detection reliability while significantly reducing overall power consumption compared to continuous monitoring.
2Measurement precision
If the ADC circuit operates at high sampling rate to avoid aliasing from nearby WiFi signals, then measurement precision is improved, but power consumption increases
Solution Approach 1:
The system dynamically changes the ADC sampling rate parameter based on the specific DFS channel being monitored. The sampling rate is set to a minimum value sufficient to avoid aliasing for each channel bandwidth, rather than using a fixed high rate for all channels. This optimization reduces ADC power consumption while maintaining adequate measurement precision for radar signal detection.
Data Source
AI summary
An apparatus for a low-power radar detection (LPRD) receiver is proposed in this disclosure. The LPRD receiver comprises an analog-to-digital converter (ADC) circuit configured to receive an analog dynamic frequency selection (DFS) signal associated with a DFS channel in a DFS frequency band to generate a digital DFS signal. The ADC circuit comprises a finite impulse response (FIR) filter circuit configured to sample the analog DFS signal at an FIR sampling rate determined based on a predetermined frequency plan associated with the DFS frequency band to generate a sampled DFS signal; and an ADC conversion circuit configured to convert the sampled DFS signal to the digital DFS signal at an ADC conversion rate that is lower than the FIR sampling rate.