Radar DMA Boundary Checking for Fast Object Detection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional radar systems, particularly in automotive applications, suffer from slow software-based processing speeds due to software overhead, necessitating faster object detection methods.
Innovation Solution
Implementing a Direct Memory Access (DMA) circuit and detection circuit in conjunction with a fast Fourier transform (FFT) to streamline processing, reducing software overhead and enabling high-speed object detection, while incorporating hardware boundary checking to ensure relevant data is processed efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If software-based processing is used in conventional radar systems, then flexibility is maintained, but processing speed becomes slow due to software overhead
Solution Approach 1:
The patent replaces software-based processing with hardware-based processing using a Field Programmable Gate Array (FPGA). The FPGA implements signal processing functions such as Fast Fourier Transform (FFT), Doppler processing, and range-Doppler mapping in hardware logic circuits, eliminating the need for software execution and associated overhead. This substitution of mechanical/software systems with hardware/electronic systems directly addresses the speed limitation while maintaining processing flexibility through programmability.
2Loss of information
If the complete radar data cube is stored in memory for processing, then all data is available for analysis, but memory requirements and processing time increase
Solution Approach 1:
The patent extracts and processes only the most relevant features from the radar data cube in real-time using FPGA-based signal processing. Instead of storing and analyzing the complete data cube, the system extracts key parameters such as range, Doppler frequency, and target detection information through hardware-implemented FFT and processing algorithms. This selective extraction reduces memory requirements and processing time while maintaining essential information for object detection.
Solution Approach 2:
The patent performs preliminary signal processing operations including range FFT, Doppler FFT, and threshold detection in the FPGA before data reaches memory. By preprocessing the radar signals and extracting meaningful information beforehand, the system reduces the volume of data that needs to be stored and further processed, thereby decreasing both memory requirements and overall processing time while preserving critical target information.
3Measurement precision
If hardware boundary checking is implemented in the DMA, then data processing accuracy is improved, but device complexity increases
Solution Approach 1:
The patent merges the boundary checking function directly into the Direct Memory Access (DMA) controller hardware. The DMA controller is enhanced with integrated logic that automatically checks data addresses and boundaries during memory transfer operations. This consolidation of boundary checking functionality within the existing DMA infrastructure improves data processing accuracy by preventing buffer overflows and address errors, while minimizing additional hardware complexity through functional integration rather than separate dedicated circuits.
Data Source
AI summary
A radar system including a direct memory access (DMA). The DMA includes a bus interface including control/status registers and data-in/data-out registers. The DMA also includes potential object queue memory coupled to the bus interface, and a potential object queue logic coupled to the potential object queue memory. The DMA also includes boundary checking circuitry configured to detect whether any portion of a DMA read configuration is greater than a maximum range bin or less than a minimum range bin. The boundary checking circuitry detects whether any portion of the DMA read configuration is greater than a maximum Doppler bin or less than a minimum Doppler bin.