Radar IC Failover Using Slave-to-Master LO Reconfiguration
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Solution Overview
Problem
In radar systems for autonomous vehicles, a failure in the master IC causes a complete malfunction of slave ICs, leading to a full failure of the radar sensor, as they rely on the master for timing control and local oscillator signals, which are no longer provided.
Innovation Solution
A radar system design where a second IC can be reconfigured from a slave mode to a master mode upon detection of a fault in the first IC, allowing it to generate its own local oscillator and clock signals, thereby maintaining at least minimal functionality by using a reference clock signal from a crystal oscillator.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple radar transceivers are cascaded to increase angular resolution and SNR, then measurement precision is improved, but reliability deteriorates because a master chip failure causes full system failure
Solution Approach 1:
The patent implements preliminary fault detection mechanisms that monitor the master chip's health status before complete failure occurs. When faults are detected early, the system proactively switches to a backup configuration, preventing total system failure and maintaining operational reliability while preserving the cascaded transceiver architecture for high measurement precision
Solution Approach 2:
The patent dynamically changes the operational parameters of the radar system by switching between master-slave configurations. When the master chip fails, the system reconfigures a previously slave transceiver to operate as master, changing the system's operational state from single-master to alternative-master configuration, thereby maintaining reliability without sacrificing the angular resolution benefits of the cascaded architecture
2Device complexity
If a master IC provides centralized control and LO signals to slave ICs, then device complexity is reduced, but reliability deteriorates as the system becomes vulnerable to single-point failures
Solution Approach 1:
The system preliminarily establishes backup control paths and redundant LO signal generation capabilities in slave ICs before failures occur. Each slave IC is pre-configured with the ability to generate LO signals and assume master control functions, creating a latent redundancy that activates only when needed, thus maintaining simplicity during normal operation while ensuring reliability during failures
Solution Approach 2:
The patent transforms the static master-slave control architecture into a dynamic system where roles can change. The control architecture adapts by allowing any slave IC to become master when needed, creating a flexible, reconfigurable system that maintains low complexity during normal operation but gains fault tolerance when reconfiguration is triggered
3Ease of operation
If slave ICs rely on master-generated LO and timing signals, then ease of operation is improved, but reliability deteriorates when the master IC fails
Solution Approach 1:
Slave ICs are preliminarily equipped with the capability to generate their own LO and timing signals, along with fault detection mechanisms. This preliminary preparation allows them to maintain synchronization simplicity during normal operation while being ready to independently generate signals if the master fails, ensuring operational continuity
Solution Approach 2:
The system implements feedback mechanisms where slave ICs monitor the health of the master IC and can detect faults in real-time. This feedback enables automatic reconfiguration where affected slave ICs can switch to using their own internally-generated LO and timing signals, maintaining ease of operation through automated synchronization while ensuring reliability through fault-tolerant operation
Data Source
AI summary
A radar system (300) and a method of operating the radar system is disclosed, the radar system (300) comprising: a first IC (310), arranged to receive a reference clock signal (380) and configurable to generate a common local oscillator signal (400) based on the reference clock signal (380); a second IC (320), arranged to receive the common local oscillator signal (400) from the first IC (310); and a controller (350), adapted to detect a fault in the first IC (310), and configured, upon detection of a fault in the first IC (310), to send at least one signal to the second IC (320) for reconfiguring the second IC (320) from a slave mode to a master mode; wherein, when operating in the slave mode, the second IC (320) is configured to use the common local oscillator signal (400) generated by the first IC (310), and, when operating in the master mode, said second IC (320) is configured to use an internally-generated local oscillator signal. The second IC (310) may be configured to receive the reference clock signal (380), wherein the internally-generated local oscillator signal is based on the reference clock signal (380).